PCI9030-AA60BI PLX Technology, PCI9030-AA60BI Datasheet - Page 169

• Manufacturer Part Number: PCI9030-AA60BI
• Description: Peripheral Drivers & Components (PCIs) 32-bit 33MHz PCI v.2.2-compliant
• Manufacturer: PLX Technology

Specifications of PCI9030-AA60BI

• Package / Case: FPBGA-180
• Maximum Operating Temperature: + 125 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 3.3 V
• Lead Free Status / Rohs Status: No RoHS Version Available

Non-Multiplexed Local Bus Mode Pinout
Table 11-12. Non-Multiplexed Bus Mode Interface Pins (Continued)
PCI 9030 Data Book Version 1.4
© 2002 PLX Technology, Inc. All rights reserved.
RD#
READY#
WR#
Total
Symbol
Read Strobe
Local Ready
Input
Write Strobe
Signal Name
Total
Pins
70
1
1
1
12 mA
12 mA
Type
Pin
TS
TS
O
O
I
PQFP Pin
Number
141
143
140
µBGA Pin Number
D10
C10
E10
General purpose read strobe. Timing is
controlled by current Bus Region Descriptor
register. Normally asserted during NRAD wait
states, unless Read Strobe Delay clocks are
programmed in bits [27:26]. Remains asserted
throughout Burst and NRDD wait states.
Local ready input indicates Read data on
the bus is valid or a Write Data transfer is
complete. READY# input is not sampled
until the internal wait state counter expires
(WAITo# de-asserted).
General purpose write strobe. Timing is
controlled by the current Bus Region Descriptor
register. Normally asserted during NWAD
wait states, unless Write Strobe Delay clocks
are programmed in bits [29:28]. Remains
asserted throughout Burst and NWDD wait
states. LAD/LD data valid time can be extended
beyond WR# de-assertion if Write Cycle Hold
clocks are programmed in bits [31:30].
Function
Pin Description
Section 11
11-17