PCI9030-AA60BI PLX Technology, PCI9030-AA60BI Datasheet - Page 170

• Manufacturer Part Number: PCI9030-AA60BI
• Description: Peripheral Drivers & Components (PCIs) 32-bit 33MHz PCI v.2.2-compliant
• Manufacturer: PLX Technology

Specifications of PCI9030-AA60BI

• Package / Case: FPBGA-180
• Maximum Operating Temperature: + 125 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 3.3 V
• Lead Free Status / Rohs Status: No RoHS Version Available

Section 11
Pin Description
11.6
The PCI 9030 provides a JTAG Boundary Scan
interface which can be utilized to debug a pin’s
connectivity to the board.
11.6.1 IEEE 1149.1 Test Access Port
The IEEE 1149.1 Test Access Port (TAP), commonly
called the JTAG (Joint Test Action Group) debug port,
is an architectural standard described in IEEE
Standard 1149.1-1990. This standard describes a
method for accessing internal chip facilities using a
four- or five-signal interface.
The JTAG debug port, originally designed to support
scan-based board testing, is enhanced to support the
attachment of debug tools. The enhancements, which
comply with IEEE Standard 1149.1-1990 for vendor-
specific extensions, are compatible with standard
JTAG hardware for boundary-scan system testing.
• JTAG Signals—JTAG debug port implements the
• JTAG Clock Requirements—The TCK signal
• JTAG Reset Requirements—JTAG debug port
11.6.2 JTAG Instructions
The JTAG debug port provides the standard
sample/preload,
instructions behave as the
are three private instructions. (Refer to Table 11-13.)
The Instruction register length is 236 bits, and
instruction length is 4 bits. The PCI 9030 does not
have an IDCODE register.
Table 11-13. JTAG Instructions
11-18
four required JTAG signals—TCK, TMS, TDI,
TDO—and the optional TRST# signal.
frequency can range from DC to one-half of the
internal chip clock frequency.
logic is reset at the same time as a system reset.
Upon receiving TRST#, the JTAG TAP controller
returns to the Test-Logic Reset state.
Sample/Preload
Instruction
Bypass
Extest
DEBUG INTERFACE
(JTAG Debug Port)
and
Input Code
bypass
0000
0100
1111
bypass
instructions.
instruction. There
IEEE Standard
Comments
1149.1-1990
Invalid
extest,
11.6.3 JTAG Boundary Scan
Boundary Scan Description Language (BSDL), IEEE
1149.1b-1994, is a supplement to IEEE Standard
1149.1-1990. BSDL, a subset of the IEEE 1076-1993
Standard VHSIC Hardware Description Language
(VHDL), allows a rigorous description of testability
features in components which comply with the
standard. It is used by automated test pattern
generation tools for package interconnect tests and
electronic
synthesized test logic and verification. BSDL supports
robust extensions that can be used for internal test
generation and to write software for hardware debug
and diagnostics.
The primary components of BSDL include the logical
port description, physical pin map, instruction set, and
boundary register description.
The logical port description assigns symbolic names to
the pins of a chip. Each pin has a logical type of in,
out, inout, buffer, or linkage that defines the logical
direction of signal flow.
The physical pin map correlates the logical ports of the
chip to the physical pins of a specific package. A
BSDL description can have several physical pin maps;
each map is given a unique name.
Instruction set statements describe the bit patterns
that must be shifted into the Instruction register to
place the chip in the various test modes defined by the
standard. Instruction set statements also support
descriptions of instructions that are unique to the chip.
The boundary register description lists each cell or
shift stage of the Boundary register. Each cell has a
unique number; the cell numbered 0 is the closest to
the Test Data Out (TDO) pin and the cell with the
highest number is closest to the Test Data In (TDI) pin.
Each cell contains additional information, including:
cell type, logical port associated with the cell, logical
function of the cell, safe value, control cell number,
disable value, and result value.
Notes:
packages may be downloaded from the PCI 9030 toolbox at
http://www.plxtech.com/products/9030.htm
Refer to PCI 9030 Errata #5, #6, and #8 for information regarding
specific JTAG issues.
The PCI 9030 BSDL files for the PQFP and µBGA
© 2002 PLX Technology, Inc. All rights reserved.
design
automation
PCI 9030 Data Book Version 1.4
(EDA)
Debug Interface
tools
for