PCI9030-AA60BI PLX Technology, PCI9030-AA60BI Datasheet - Page 30

• Manufacturer Part Number: PCI9030-AA60BI
• Description: Peripheral Drivers & Components (PCIs) 32-bit 33MHz PCI v.2.2-compliant
• Manufacturer: PLX Technology

Specifications of PCI9030-AA60BI

• Package / Case: FPBGA-180
• Maximum Operating Temperature: + 125 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 3.3 V
• Lead Free Status / Rohs Status: No RoHS Version Available

Section 2
PCI and Local Bus
2.2.3.2.2
2.2.3.2.2.1
LA[27:2] contains the transfer address. The address
remains valid during the transfer, and increments with
successive data during Burst cycles.
2.2.3.2.2.2
The LD[31:0] bus is a 32-bit Non-Multiplexed Data
Bus. During Data phases, LD[31:0], LD[15:0], or
LD[7:0] contain transfer data for a 32-, 16-, or 8-bit
bus, respectively. If the bus is 8 or 16 bits wide, the
data supplied by the PCI 9030 is replicated across the
entire 32-bit-wide bus.
2.2.3.3
The control/status signals control the address latches
and flow of data across the Local Bus.
2.2.3.3.1
A Local Bus access starts when ADS# (address
strobe) is asserted during an address state by the
PCI 9030 as the Local Bus Master. ALE is used
to strobe the LA/LAD Bus into an external address
latch. When BTERM# input is enabled for a Local
Address space in the corresponding Bus Region
Descriptor register, BTERM# can be used to complete
an access in place of LRDYi#. When BTERM# is
enabled and asserted, LRDYi# is ignored. (Refer to
Figure
specifications, and to Section 2.2.4.3 for further
information regarding BTERM#.)
2-4
12-3
Control/Status
Non-Multiplexed Mode
(MODE=0)
ADS#, ALE
on
LA[27:2]
LD[31:0]
page
12-5
for
ALE
timing
2.2.3.3.2
During an Address phase, the LBE[3:0]# Local Byte
Enables denote which byte lanes are being used
during access of a 32-bit bus. They remain asserted
until the end of the data transfer.
2.2.3.3.3
When the PCI 9030 owns the Local Bus, LLOCKo# is
asserted to indicate that an atomic operation for a PCI
Target access may require multiple transactions to
complete. LLOCKo# is asserted during the Address
phase of the first transaction of the atomic operation,
and de-asserted one clock after the last transaction of
the atomic operation completes. If enabled, the Local
Bus arbiter does not grant the Bus to another Master
until the atomic operation completes.
2.2.3.3.4
During an Address phase, LW/R# is driven to a valid
state, and signifies direction of the data transfer. Since
the PCI 9030 is the Local Bus Master, LW/R# is driven
high when the PCI 9030 is writing data to a Local Bus,
and low when it is reading the bus.
2.2.3.3.5
RD# is a general purpose read output strobe. The
timing is controlled by the current Bus Region
Descriptor register. The RD# strobe is asserted during
the entire data transfer.
Normally, RD# is also asserted during NRAD
wait states, unless Read Strobe Delay clocks are
programmed the Bus Region Descriptor register(s)
(LASxBRD[27:26] and/or EROMBRD[27:26], where x
is the Local Address Space number). (Refer to Table
2-5 and Figure 2-3.) RD# remains asserted throughout
Burst and NRDD wait states.
© 2002 PLX Technology, Inc. All rights reserved.
LBE[3:0]#
LLOCKo#
LW/R#
RD#
PCI 9030 Data Book Version 1.4
Local Bus