PCI9030-AA60BI PLX Technology, PCI9030-AA60BI Datasheet - Page 34

• Manufacturer Part Number: PCI9030-AA60BI
• Description: Peripheral Drivers & Components (PCIs) 32-bit 33MHz PCI v.2.2-compliant
• Manufacturer: PLX Technology

Specifications of PCI9030-AA60BI

• Package / Case: FPBGA-180
• Maximum Operating Temperature: + 125 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 3.3 V
• Lead Free Status / Rohs Status: No RoHS Version Available

Section 2
PCI and Local Bus
2.2.4.2
The PCI 9030 as a Local Bus Master signals internal
wait states with the WAITo# signal. Local Bus devices
can insert external wait states by delaying READY#
assertion. (Refer to Figure 2-2 and Figure 2-3.) The
following figure illustrates wait state control.
Figure 2-4. Wait States
Note:
2.2.4.2.1
The Local Address Space Bus Region Descriptor can
be used to program the number of wait states (if any)
generated by the internal wait state generator. (Refer
to Table 2-5.)
Table 2-5. Local Address Space Bus Region Descriptor Internal Wait States
2-8
Note:
IRDY# for wait states or
simply ends the cycle
TRDY# when waiting
PCI 9030 de-asserts
Accessing PCI 9030
PCI Bus de-asserts
when it is not ready
PCI Bus
on the Local Bus
The figure represents a sequence of Bus cycles.
x is the Local Address Space number.
from PCI Bus
Wait State
Wait State Control
Internal Wait State Generator
NWAD
NWDD
NRDD
NRAD
NXDA
9030
PCI
PCI 9030
accessing Local Bus
PCI 9030 generates wait
states with WAITo#
(programmable)
Local Bus can respond
to PCI 9030 requests
with READY#
EROMBRD[12:11]
EROMBRD[14:13]
EROMBRD[19:15]
EROMBRD[21:20]
Local Bus
EROMBRD[10:6]
LASxBRD[12:11]
LASxBRD[14:13]
LASxBRD[19:15]
LASxBRD[21:20]
LASxBRD[10:6]
Bits
NXDA wait states are inserted only after the last Data
transfer of a Bus request. For example, for a PCI
Target single Cycle access to an 8-bit burst Local Bus,
NXDA wait states are inserted only after the fourth
byte, rather than after every byte.
2.2.4.2.2
If READY# mode is disabled, the external READY#
input signal has no effect on wait states for a Local
access. Wait states between Data cycles are inserted
internally by a wait state counter. The wait state
counter is initialized with its Configuration register
value at the start of each Data access.
If READY# mode is enabled and the internal wait state
counter is zero (default value), the READY# input
controls the number of additional wait states.
If READY# mode is enabled and the internal wait state
counter is programmed to a non-zero value, READY#
has no effect until the wait state counter reaches 0.
When it reaches 0, the READY# input controls the
number of additional wait states.
BTERM# input can also be used as a ready input.
(Refer to Section 2.2.4.3.) If the internal wait state
counter is programmed to a non-zero value and
BTERM# is enabled, BTERM# input is not sampled
until the wait state counter reaches 0.
Number of Read Address-to-Data wait states (0-31). (Wait
states between the Address cycle and first Read Data cycle.)
Number of Read Data-to-Data wait states (0-3). (Wait states
between consecutive Data cycles of a Burst read.)
Number of Read/Write Data-to-Address wait states (0-3).
LAD/LD Bus Write data is not valid during NXDA wait states.
(Wait states between consecutive bus requests. NXDA
wait states are inserted only after the last Data transfer
of a PCI Target access.)
Number of Write Address-to-Data wait states (0-31). LAD/
LD Bus data is valid during NWAD wait states. (Wait states
between the Address cycle and first Write Data cycle.)
Number of Write Data-to-Data wait states (0-3). (Wait states
between consecutive Data cycles of a Burst write.)
© 2002 PLX Technology, Inc. All rights reserved.
Ready Signaling
Description
PCI 9030 Data Book Version 1.4
Local Bus