PCI9030-AA60BI PLX Technology, PCI9030-AA60BI Datasheet - Page 167

• Manufacturer Part Number: PCI9030-AA60BI
• Description: Peripheral Drivers & Components (PCIs) 32-bit 33MHz PCI v.2.2-compliant
• Manufacturer: PLX Technology

Specifications of PCI9030-AA60BI

• Package / Case: FPBGA-180
• Maximum Operating Temperature: + 125 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 3.3 V
• Lead Free Status / Rohs Status: No RoHS Version Available

Non-Multiplexed Local Bus Mode Pinout
11.5
Table 11-12. Non-Multiplexed Bus Mode Interface Pins
PCI 9030 Data Book Version 1.4
© 2002 PLX Technology, Inc. All rights reserved.
ADS#
ALE
BLAST#
BTERM#
GPIO4
LA27
GPIO5
LA26
GPIO6
LA25
GPIO7
LA24
Symbol
NON-MULTIPLEXED LOCAL BUS MODE PINOUT
Address Strobe
Address Latch
Enable
Burst Last
Burst
Terminate
General
Purpose I/O 4
Address Bus
General
Purpose I/O 5
Address Bus
General
Purpose I/O 6
Address Bus
General
Purpose I/O 7
Address Bus
Signal Name
Total
Pins
1
1
1
1
1
1
1
1
12 mA
12 mA
12 mA
12 mA
12 mA
12 mA
12 mA
Type
Pin
I/O
I/O
I/O
I/O
TS
TS
TS
TS
TS
TS
TS
O
O
O
I
PQFP Pin
Number
138
139
144
137
136
135
134
75
µBGA Pin Number
C11
C12
B11
B10
A12
A13
B12
M9
Indicates a valid address and start of a new
Bus access. Asserted for the first clock of
a Bus access.
Asserted during the Address phase and
de-asserted before the Data phase.
Driven by the current Local Bus Master to
indicate the last transfer in a Bus access.
If Bterm mode (continuous burst) and BTERM#
input are disabled (LASxBRD[2]=0 and/or
EROMBRD[2]=0), the PCI 9030 also bursts
up to four Lwords. If enabled, the PCI 9030
continues to burst until BTERM# input is
asserted or the burst completes. BTERM# is
a Ready input that breaks up a Burst cycle and
causes another Address cycle to occur. Used
in conjunction with the PCI 9030 programmable
wait state generator.
Can be programmed to a configurable general
purpose I/O pin, GPIO4, or as Address Bus
output pin, LA27.
Default functionality is LA27. Pin configuration
occurs when the serial EEPROM contents are
loaded following PCI reset, or upon subsequent
writing to the GPIOC[13:12] register bits.
Can be programmed to a configurable general
purpose I/O pin, GPIO5, or as Address Bus
output pin, LA26.
Default functionality is LA26. Pin configuration
occurs when the serial EEPROM contents are
loaded following PCI reset, or upon subsequent
writing to the GPIOC[16:15] register bits.
Can be programmed to a configurable general
purpose I/O pin, GPIO6, or as Address Bus
output pin, LA25.
Default functionality is LA25. Pin configuration
occurs when the serial EEPROM contents are
loaded following PCI reset, or upon subsequent
writing to the GPIOC[19:18] register bits.
Can be programmed to a configurable general
purpose I/O pin, GPIO7, or as Address Bus
output pin, LA24.
Default functionality is LA24. Pin configuration
occurs when the serial EEPROM contents are
loaded following PCI reset, or upon subsequent
writing to the GPIOC[22:21] register bits.
Function
Pin Description
Section 11
11-15