PCI9030-AA60BI PLX Technology, PCI9030-AA60BI Datasheet - Page 23

• Manufacturer Part Number: PCI9030-AA60BI
• Description: Peripheral Drivers & Components (PCIs) 32-bit 33MHz PCI v.2.2-compliant
• Manufacturer: PLX Technology

Specifications of PCI9030-AA60BI

• Package / Case: FPBGA-180
• Maximum Operating Temperature: + 125 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 3.3 V
• Lead Free Status / Rohs Status: No RoHS Version Available

Company and Product Background
Figure 1-3 illustrates a typical PMC adapter card.
Figure 1-3. Typical PMC Adapter Card
1.1.4
1.1.4.1
PCI r2.2 Compliant. This 32-bit, 33 MHz Target
Interface Chip enables PCI Burst Transfers up to
132 MB/s.
Up to 60 MHz Local Bus Operation. Enables burst
transfers up to 240 MB/s.
PCI Target Read Ahead Mode. Prefetches a
programmable amount of data from the Local Bus. This
data can then be burst-transferred onto the PCI bus
from the PCI 9030 internal PCI Target Read FIFO. The
prefetch size can be programmed to match the PCI
master burst length or can be used in the PCI Target
Read Ahead mode data. This feature also allows for
increased bandwidth and reduced read latency.
PCI Target Programmable Burst. The PCI 9030 may
be programmed for several burst lengths, including
unlimited burst. This allows for maximum transfer rates
on both the PCI and Local Buses.
PCI Target Delayed Write Mode. The PCI Target
Write data accumulates in the PCI Target Write FIFO to
allow uninterrupted burst transactions on the Local
Bus. This allows for a higher throughput for conditions
in which the PCI Clock frequency is slower than the
Local Clock frequency.
Posted Memory Writes. A PCI Memory write is posted
to the PCI 9030 for later transfer to the Local Bus. This
allows for maximum PCI performance and avoids
potential deadlock situations.
PCI 9030 Data Book Version 1.4
© 2002 PLX Technology, Inc. All rights reserved.
PCI 9030 SMARTarget Features
Performance Features
SMARTarget
Memory
PCI 9030
( BGA)
Device
32-Bit 60 MHz Local Bus
™
I/O
1.1.4.2
Programmable Local Bus. Operates up to 60 MHz
and supports both Multiplexed and Non-Multiplexed
32-bit address/data protocol, and dynamic Local Bus
width control allowing Slave accesses to 8-, 16- or
32-bit devices.
PCI-to-Local Address Spaces. Supports five PCI-to-
Local Address spaces. Spaces 0, 1, 2, 3, and the
Expansion ROM all allow a PCI Bus Master to access
the
programmable wait states, bus width, and burst
capabilities.
GPIOs. The PCI 9030 has nine programmable general
purpose I/O pins, which may be used for generic
interface purposes.
Four Programmable Chip
decode logic, which improves performance.
PICMG 2.1, R2.0 Hot Swap Silicon. Compliant with
PICMG 2.1, R2.0, including support for Programming
Interface 0 (PI = 0), Precharge Bias Voltage, and Early
Power.
Big/Little Endian Conversion. Supports automatic
on-the-fly Big Endian and Little Endian conversion for
all operations and bus widths.
Interrupt Generator/Controller. Can assert PCI
interrupts from external and internal sources.
VPD Support. Fully supports the PCI r2.2 Vital Product
Data (VPD) extension, including the New Capabilities
Structure. Provides an alternate access method for
user- or system-defined parameters or configuration
data.
PCI Power Management. Supports D
power states.
Two Programmable FIFOs for Zero Wait State Burst
Operation. The following table describes the FIFO
depth.
Table 1-1. FIFO Depth
3.3/5V Tolerant PCI Signaling. Enables Universal
PCI Adapters.
3.3V CMOS Device in 176-pin PQFP or 180-pin
µBGA.
Local
PCI Target Read
PCI Target Write
FIFO
Flexibility Features
Memory
spaces
Selects. Eliminates
with
16 Lwords
32 Lwords
Depth
0
Introduction
individually
and D
Section 1
3hot
1-3