PCI9030-AA60BI PLX Technology, PCI9030-AA60BI Datasheet - Page 27

• Manufacturer Part Number: PCI9030-AA60BI
• Description: Peripheral Drivers & Components (PCIs) 32-bit 33MHz PCI v.2.2-compliant
• Manufacturer: PLX Technology

Specifications of PCI9030-AA60BI

• Package / Case: FPBGA-180
• Maximum Operating Temperature: + 125 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 3.3 V
• Lead Free Status / Rohs Status: No RoHS Version Available

2
This section discusses PCI and Local Bus operation.
2.1
2.1.1
The PCI 9030 is PCI r2.2-compliant. Refer to PCI r2.2
for specific PCI Bus functions as a PCI Target
Interface chip.
2.1.1.1
As a Target, the PCI 9030 allows access to the
PCI 9030 internal registers and the Local Bus, using
the commands listed in Table 2-1.
All Read or Write accesses to the PCI 9030 can be
Byte, Word, or Lword (32-bit data). All memory
commands are aliased to basic memory commands.
All PCI 9030 I/O accesses are decoded to an Lword
boundary. Byte enables are used to determine which
bytes are read or written. An I/O access with
illegal byte enable combinations is terminated with
a Target Abort.
Table 2-1. PCI Target Command Codes
2.1.1.2
The PCI Bus Master throttles IRDY# and the PCI Bus
Slave throttles TRDY# to assert PCI Bus wait state(s).
PCI 9030 Data Book Version 1.4
© 2002 PLX Technology, Inc. All rights reserved.
Memory Write and Invalidate
Memory Read Multiple
Configuration Read
Configuration Write
Command Type
Memory Read Line
Memory Read
Memory Write
PCI AND LOCAL BUS
PCI BUS
PCI Bus Interface and Bus Cycles
I/O Read
I/O Write
PCI Target Command Codes
Wait States—PCI Bus
Code (C/BE[3:0]#)
1010 (Ah)
1011 (Bh)
1100 (Ch)
1110 (Eh)
1111 (Fh)
0010 (2h)
0011 (3h)
0110 (6h)
0111 (7h)
2.1.1.3
The PCI Bus is a Little Endian bus (that is, the address
is invariant and data is Lword-aligned to the lowermost
byte lane).
Table 2-2. PCI Bus Little Endian Byte Lanes
2.1.1.4
PCI Memory Address spaces assigned to the
PCI 9030 for its Local Address spaces can be mapped
as either prefetchable or non-prefetchable memory
within the system. Configuration software (PCI BIOS)
checks
Prefetchable bit(s) (PCIBARx[3], where x is the PCI
Base Address register number) to determine whether
the Target memory is prefetchable. The value of the
PCIBARx[3]
Configuration register settings (as configured by serial
EEPROM values) at boot time.
When set to 1, the PCIBARx[3] bit(s) signals that the
Memory space can operate under a prefetching
protocol, for improved performance. If a PCI Master
initiates a Read to a location that is mapped in the
prefetchable
PCI-to-PCI bridge is permitted to extend the Read
Transaction burst length in anticipation of the Master
consuming the additional data. PCIBARx[3] should
normally be set if all the following conditions are met:
• Multiple Memory reads of an Lword result
• If Read data is discarded by the PCI Master,
• Address space is not mapped as I/O
• Local Target must be able to operate with
in the same data
no negative side effects occur
byte merging
Byte Number
the
0
1
2
3
PCI Prefetchable
Memory Mapping
PCI Bus Little Endian Mode
bit(s)
address
PCI 9030
is
range,
set
Configuration
according
Byte Lane
a
AD[23:16]
AD[31:24]
AD[15:8]
AD[7:0]
Host-to-PCI
to
register
Local
2-1
or