PCI9030-AA60BI PLX Technology, PCI9030-AA60BI Datasheet - Page 166

• Manufacturer Part Number: PCI9030-AA60BI
• Description: Peripheral Drivers & Components (PCIs) 32-bit 33MHz PCI v.2.2-compliant
• Manufacturer: PLX Technology

Specifications of PCI9030-AA60BI

• Package / Case: FPBGA-180
• Maximum Operating Temperature: + 125 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 3.3 V
• Lead Free Status / Rohs Status: No RoHS Version Available

Section 11
Pin Description
Table 11-11. Multiplexed Bus Mode Interface Pins (Continued)
11-14
LW/R#
RD#
READY#
WR#
Total
Symbol
Write/Read
Read Strobe
Local Ready
Input
Write Strobe
Signal Name
Total
Pins
70
1
1
1
1
12 mA
12 mA
12 mA
Type
Pin
TS
TS
TS
O
O
O
I
PQFP Pin
Number
142
141
143
140
µBGA Pin
Number
D10
C10
A11
E10
© 2002 PLX Technology, Inc. All rights reserved.
Asserted low for reads and high for writes.
General purpose read strobe. Timing is controlled
by current Bus Region Descriptor register.
Normally asserted during NRAD wait states,
unless Read Strobe Delay clocks are
programmed in bits [27:26]. Remains asserted
throughout Burst and NRDD wait states.
Local ready input indicates Read data is on
the Local Bus, or that Write data is accepted.
READY# input is not sampled until internal wait
states expire [WAITo# de-asserted, provided
GPIO0/WAITo# is configured as WAITo#
(GPIOC[0]=1)]. READY# is ignored when
BTERM# is enabled and asserted.
General purpose write strobe. Timing is
controlled by the current Bus Region Descriptor
register. Normally asserted during NWAD
wait states, unless Write Strobe Delay clocks are
programmed in bits [29:28]. Remains asserted
throughout Burst and NWDD wait states. LAD/LD
data valid time can be extended beyond WR#
de-assertion if Write Cycle Hold clocks are
programmed in bits [31:30].
Multiplexed Local Bus Mode Pinout
PCI 9030 Data Book Version 1.4
Function