PCI9030-AA60BI PLX Technology, PCI9030-AA60BI Datasheet - Page 100

• Manufacturer Part Number: PCI9030-AA60BI
• Description: Peripheral Drivers & Components (PCIs) 32-bit 33MHz PCI v.2.2-compliant
• Manufacturer: PLX Technology

Specifications of PCI9030-AA60BI

• Package / Case: FPBGA-180
• Maximum Operating Temperature: + 125 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 3.3 V
• Lead Free Status / Rohs Status: No RoHS Version Available

Section 6
Interrupts and General Purpose I/O
INTA# is a level output. If INTA# is asserted or
de-asserted in response to LINTi[2:1] input, INTA#
output timing is asynchronous to the PCI and Local
clocks. If INTA# is asserted or de-asserted by
software, INTA# output timing is referenced to a rising
edge of the PCI clock.
Note: Regarding PLXMon, if PCI interrupts are enabled and the
PCI 9030 generates an INTA#, the interrupt status displayed in
PLXMon does not show the bit in the INTCSR control register as
“active.” This occurs because the PCI 9030 driver responds to the
PCI interrupt and clears it. To test a PCI interrupt assertion and view
active status with PLXMon, disable the PCI Interrupt Enable bit
(INTCSR[6]=0), while keeping all other bit(s) required to generate
the interrupt active. Then the driver does not see an INTA#
assertion. After the screen is refreshed, following interrupt assertion,
the active status can be seen in PLXMon.
6.2.2
The PCI 9030 provides two local interrupt input pins
LINTi[2:1]. The Local interrupts can be used to
generate a PCI interrupt, and/or software can poll the
interrupt status bits (INTCSR[5,2]). LINTi[2:1] are
programmable for active-low or active-high polarity
(INTCSR[4, 1], respectively) in the default Level-
Sensitive mode (INTCSR[9, 8]=00). Each pin can be
optionally configured as a rising edge-triggered
interrupt (INTCSR[8, 1, 0]=111 and INTCSR[9, 4, 3]
=111), such as, for ISA compatibility. Level-sensitive
interrupts are cleared when the interrupt source is no
longer active, or the interrupt input pin is disabled.
Edge-triggered (latched) interrupts remain active until
cleared by a software write, which asserts the
associated Interrupt Clear register bit(s) (INTCSR[11,
10]=11),
(INTCSR[3, 0]=00). If the PCI Interrupt Enable bit is
set (INTCSR[6]=1) and INTA# is asserted for a Local
interrupt input assertion, INTA# can be de-asserted by
clearing the PCI Interrupt Enable bit (INTCSR[6]=0).
PCI 9030 sampling of enabled LINTi[2:1] inputs, and
INTA# output state changes (if PCI interrupts are
enabled) in response to enabled LINT[2:1] input, are
asynchronous to the PCI and Local clocks.
6-2
Local Interrupt Input (LINTi[2:1])
or
disables
the
interrupt
input
pin
6.2.3
The PCI 9030 is a PCI Target device only; therefore,
there is no access to the internal registers from the
Local Bus. The Local Power Management Interrupt
output (LPMINT#) is included to accommodate the
PCI Bus Power Management interface to a Local Bus.
The PCI 9030 asserts LPMINT# to request a Power
State change to the Local Bus when the Power State
bit(s) change (PMCSR[1:0]). The LPMINT# interrupt is
synchronous to the Local clock. When asserted, it is a
one clock-wide pulse.
External glue logic is needed to latch the Power State
change and to retain the previous Power State history
for further evaluation by the external Local Bus
Initiator.
6.2.4
The Local Power Management Enumerator Set
Interrupt
accommodate the PCI Bus Power Management
interface to a Local Bus.
The external Local Bus Initiator can assert LPMESET
to the PCI 9030 Power Management Control/Status
register (PMCSR[15]) to set the PME# status and
assert the PME# signal to the PCI Bus in case of a
Wake-up Request event.
6.2.5
The PCI 9030 asserts a SERR# pulse if parity
checking is enabled (PCICR[6]=1) and it detects an
address parity error.
The SERR# output can be enabled or disabled with
the SERR# Enable bit (PCICR[8]).
Local Power Management
Interrupt (LPMINT#)
Local Power Management
Enumerator Set
All Modes PCI SERR# (PCI NMI)
© 2002 PLX Technology, Inc. All rights reserved.
input
(LPMESET)
PCI 9030 Data Book Version 1.4
is
included
Interrupts
to