PCI9030-AA60BI PLX Technology, PCI9030-AA60BI Datasheet - Page 132

no-image

PCI9030-AA60BI

Manufacturer Part Number
PCI9030-AA60BI
Description
Peripheral Drivers & Components (PCIs) 32-bit 33MHz PCI v.2.2-compliant
Manufacturer
PLX Technology
Datasheets

Specifications of PCI9030-AA60BI

Package / Case
FPBGA-180
Maximum Operating Temperature
+ 125 C
Minimum Operating Temperature
- 40 C
Mounting Style
SMD/SMT
Operating Supply Voltage
3.3 V
Lead Free Status / Rohs Status
No RoHS Version Available

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
PCI9030-AA60BI
Quantity:
1 400
Part Number:
PCI9030-AA60BI
Manufacturer:
PLX
Quantity:
250
Part Number:
PCI9030-AA60BI
Manufacturer:
XILINX
0
Part Number:
PCI9030-AA60BI F
Manufacturer:
FUJI
Quantity:
4 300
Part Number:
PCI9030-AA60BIF
Manufacturer:
PLX
Quantity:
1 400
Part Number:
PCI9030-AA60BIF
Manufacturer:
PLX
Quantity:
246
Part Number:
PCI9030-AA60BIF
Manufacturer:
PLX
Quantity:
20 000
Section 10
Registers
Register 10-42. (EROMRR; 10h) Expansion ROM Range
10-18
27:11
31:28
10:1
Bit
0
Address Decode Enable. Bit 0 can only be enabled from the serial EEPROM.
To disable, set the PCI Expansion ROM Address Decode Enable bit to 0
(PCIERBAR[0]=0).
Reserved.
Specifies which PCI Address bits to use for decoding a PCI-to-Local Bus
Expansion ROM. Each bit corresponds to a PCI Address bit. Bit 27
corresponds to address bit 27. Write 1 to all bits that are to be included
in decode and 0 to all others (used in conjunction with PCIERBAR). Default is
64 KB; minimum range, if enabled, is 2 KB, and maximum range allowed by
PCI r2.2 is 16 MB.
Note:
value” is two’s complement of range.
EROMRR should normally be programmed by way of the serial EEPROM
to a value of 0h, unless Expansion ROM is present on the Local Bus. If the
value is not 0h (default value is 64 KB), system BIOS may attempt to allocate
Expansion ROM address space and then access it at the local base address
specified in EROMBA (default value is 1 MB) to determine whether the
Expansion ROM image is valid. If the image is not valid, as defined in Section
6.3.1.1 (PCI Expansion ROM Header Format) of PCI r2.2, the system BIOS
unmaps the Expansion ROM address space it initially allocated, by writing 0h
to PCIERBAR[31:0].
Reserved. (PCI Address bits [31:28] are always included in decoding.)
Range (not Range register) must be power of 2. “Range register
Description
© 2002 PLX Technology, Inc. All rights reserved.
Read
Yes
Yes
Yes
Yes
Local Configuration Registers
PCI 9030 Data Book Version 1.4
EEPROM
Write
Serial
Only
Yes
Yes
No
1111111111110
Value after
Reset
0000
1111
0h
0

Related parts for PCI9030-AA60BI