PCI9030-AA60BI PLX Technology, PCI9030-AA60BI Datasheet - Page 162

• Manufacturer Part Number: PCI9030-AA60BI
• Description: Peripheral Drivers & Components (PCIs) 32-bit 33MHz PCI v.2.2-compliant
• Manufacturer: PLX Technology

Specifications of PCI9030-AA60BI

• Package / Case: FPBGA-180
• Maximum Operating Temperature: + 125 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 3.3 V
• Lead Free Status / Rohs Status: No RoHS Version Available

Section 11
Pin Description
Table 11-10. Local Bus Mode Independent Interface Pins (Continued)
11-10
GPIO8
LCLK
LEDon#
LGNT
LINTi1
LINTi2
Symbol
General
Purpose I/O 8
Local Bus Clock
LED On
Local Bus Grant
Local Interrupt
Input 1
Local Interrupt
Input 2
Signal Name
Total
Pins
1
1
1
1
1
1
12 mA
24 mA
12 mA
Type
Pin
OD
I/O
TS
TP
O
O
I
I
I
PQFP Pin
Number
145
150
152
153
94
52
µBGA Pin
Number
L12
C8
E9
K5
A9
B8
© 2002 PLX Technology, Inc. All rights reserved.
Configurable general purpose I/O pin.
Local clock, up to 60 MHz, and may be
asynchronous to PCI clock.
Hot Swap board indicator LED. LEDon# is
controlled by the LED Software On/Off Switch
bit (HS_CSR[3]) and is also asserted during
PCI reset.
Asserted by PCI 9030 to grant control of
the Local Bus to a Local Bus Master. When
the PCI 9030 requires the Local Bus, it can
optionally signal a preempt by de-asserting
LGNT, if the Disconnect with Flush Read FIFO
bit is clear (CNTRL[31]=0) (default).
When enabled (INTCSR[0]=1) and asserted,
the LINTi1 status bit sets (INTCSR[2]=1). If the
PCI Interrupt Enable bit is set (INTCSR[6]=1),
then INTA# asserts. LINTi1 is programmable
for active-low or active-high polarity in
INTCSR[1] in the default Level-Sensitive
mode (INTCSR[8]=0). Can be optionally
configured as a positive edge-triggered interrupt
(INTCSR[8, 1, 0]=111) such as in the case of
ISA compatibility. Level-sensitive interrupts are
cleared when the interrupt source is no longer
active, or LINTi1 is disabled. An edge-triggered
interrupt is set and latched by a LINTi1
low-to-high transition, and cleared by setting
the LINTi1 Local Edge Triggerable Interrupt
Clear bit (INTCSR[10]=1).
When enabled (INTCSR[3]=1) and asserted, the
LINTi2 Status bit sets (INTCSR[5]=1). If the PCI
Interrupt Enable bit is also set (INTCSR[6]=1),
then INTA# asserts. LINTi2 is programmable for
active-low or active-high polarity in INTCSR[4]
in the default Level-Sensitive mode
(INTCSR[9]=0). Can be optionally configured
as a positive edge-triggered interrupt
(INTCSR[9, 4, 3]=111), such as in the case of
ISA compatibility. Level-sensitive interrupts are
cleared when the interrupt source is no longer
active, or LINTi2 is disabled. An edge-triggered
interrupt is set and latched by a LINTi2
low-to-high transition, and cleared by setting the
LINTi2 Local Edge Triggerable Interrupt Clear bit
(INTCSR[11]=1).
Pinout Common to All Bus Modes
PCI 9030 Data Book Version 1.4
Function