PCI9030-AA60BI PLX Technology, PCI9030-AA60BI Datasheet - Page 118

• Manufacturer Part Number: PCI9030-AA60BI
• Description: Peripheral Drivers & Components (PCIs) 32-bit 33MHz PCI v.2.2-compliant
• Manufacturer: PLX Technology

Specifications of PCI9030-AA60BI

• Package / Case: FPBGA-180
• Maximum Operating Temperature: + 125 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 3.3 V
• Lead Free Status / Rohs Status: No RoHS Version Available

Section 10
Registers
10.3
All registers may be written to or read from in Byte, Word, or Lword accesses.
Register 10-1. (PCIIDR; PCI:00h) PCI Configuration ID
Register 10-2. (PCICR; PCI:04h) PCI Command
10-4
31:16
15:10
15:0
Bit
Bit
0
1
2
3
4
5
6
7
8
9
PCI CONFIGURATION REGISTERS
Vendor ID. Identifies manufacturer of device. Defaults to the PCI SIG-issued
Vendor ID of PLX (10B5h) if blank or if no serial EEPROM is present.
Device ID. Identifies particular device. Defaults to PLX part number for
PCI interface chip (9030h) if blank or no serial EEPROM is present.
I/O Space. Writing 1 allows the device to respond to I/O Space accesses.
Writing 0 disables the device from responding to I/O Space accesses.
Memory Space. Writing 1 allows the device to respond to Memory Space
accesses. Writing 0 disables the device from responding to Memory Space
accesses.
Master Enable. Not Supported.
Special Cycle. Not Supported.
Memory Write and Invalidate Enable. Not Supported.
VGA Palette Snoop. Not Supported.
Parity Error Response. Writing 0 indicates parity error is ignored and the
operation continues. Writing 1 indicates parity checking is enabled.
Stepping Control. Controls whether a device does address/data stepping.
Writing 0 indicates the device never does stepping. Writing 1 indicates the
device always does stepping.
Note:
SERR# Enable. Writing 1 enables SERR# driver. Writing 0 disables SERR#
driver.
Fast Back-to-Back Enable. Indicates what type of fast back-to-back transfers
a Master can perform on the bus. Writing 1 indicates fast back-to-back
transfers can occur to any agent on the bus. Writing 0 indicates fast back-to-
back transfers can occur only to the same agent as in the previous cycle.
Note:
Reserved.
Hardwired to 0.
Hardwired to 0.
Description
Description
© 2002 PLX Technology, Inc. All rights reserved.
Read
Read
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
PCI 9030 Data Book Version 1.4
PCI Configuration Registers
EEPROM
EEPROM
Write
Write
Serial
Serial
Yes
Yes
Yes
Yes
No
No
No
No
No
No
No
Value after
Value after
Reset
Reset
10B5h
9030h
0h
0
0
0
0
0
0
0
0
0
0