PCI9030-AA60BI PLX Technology, PCI9030-AA60BI Datasheet - Page 49

• Manufacturer Part Number: PCI9030-AA60BI
• Description: Peripheral Drivers & Components (PCIs) 32-bit 33MHz PCI v.2.2-compliant
• Manufacturer: PLX Technology

Specifications of PCI9030-AA60BI

• Package / Case: FPBGA-180
• Maximum Operating Temperature: + 125 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 3.3 V
• Lead Free Status / Rohs Status: No RoHS Version Available

4
Functional operation described can be modified
through
registers.
4.1
PCI Target (Direct Slave) operations originate on the
PCI Bus, go through the PCI 9030, and finally access
the Local Bus. The PCI 9030 is a PCI Bus target and a
Local Bus master.
4.2
The PCI 9030 supports PCI Target accesses to Local
Memory or I/O Transfer mode.
4.2.1
The
Transfer accesses and I/O-Mapped, Single-Transfer
accesses to the Local Bus from the PCI Bus through a
16-Lword (64-byte) PCI Target Read FIFO and a
32-Lword (128-byte) PCI Target Write FIFO. The PCI
Base Address registers are provided to set up the
adapter location in the PCI memory and I/O space. In
addition, Local Mapping registers allow address
translation from the PCI Address Space to the Local
Address Space. Five spaces are available:
• Space 0
• Space 1
• Space 2
• Space 3
• Expansion ROM
Expansion ROM is intended to support a bootable
ROM device for the Host.
For single cycle PCI Target reads, the PCI 9030 reads
a single Local Bus Lword or partial Lword. The
PCI 9030 disconnects after one transfer for all
PCI Target I/O accesses.
PCI 9030 Data Book Version 1.4
© 2002 PLX Technology, Inc. All rights reserved.
PCI 9030
PCI TARGET (DIRECT SLAVE) OPERATION
OVERVIEW
DIRECT DATA TRANSFER MODE
PCI Target Operation (PCI
Master-to-Local Bus Access)
the
PCI 9030
supports
programmable
Burst
Memory-Mapped
internal
For highest data-transfer rates, the PCI 9030 supports
posted writes. Memory-mapped address spaces can
be selectively enabled to prefetch data to support PCI
Burst reads. A Prefetch Counter for each Local
address space controls whether prefetch is enabled
and continuous, or limited to a finite number of
accesses. (Refer to Section 4.2.1.3.)
If prefetch is enabled for a Local address space, the
PCI 9030 can also be programmed to support PCI
Target Read Ahead mode. (Refer to Section 4.2.1.4.)
Each Local space can be programmed to operate in
an 8-, 16-, or 32-bit Local Bus width. The PCI 9030
contains an internal wait state generator and external
wait state input, READY#. READY# can be selectively
enabled or disabled for each local address space in
the corresponding LASxBRD and/or EROMBRD
registers.
With or without wait state(s), the Local Bus,
independent of the PCI Bus, can:
• Burst as long as data is available
• Burst four data at a time (Burst-4 mode)
• Perform continuous single cycles
4.2.1.1
The
Exclusive accesses (locked atomic operations). A
PCI-locked operation to the Local Bus results in the
entire address Spaces 0, 1, 2, and 3, and Expansion
ROM being locked until they are released by the PCI
Bus Master. Locked operations are enabled or disabled
with the PCI Target LOCK# Enable bit (CNTRL[23]) for
PCI-to-Local accesses.
It is the responsibility of external arbitration logic to
monitor the LLOCKo# pin and enforce the meaning for
an atomic operation. For example, if a local master
initiates a locked operation, the Local Bus Arbiter may
choose to not grant use of the Local Bus to other
masters until the locked operation completes.
(Continuous Burst mode)
PCI 9030
PCI Target Lock
supports
direct
PCI-to-Local-Bus
4-1