PCI9030-AA60BI PLX Technology, PCI9030-AA60BI Datasheet - Page 51

• Manufacturer Part Number: PCI9030-AA60BI
• Description: Peripheral Drivers & Components (PCIs) 32-bit 33MHz PCI v.2.2-compliant
• Manufacturer: PLX Technology

Specifications of PCI9030-AA60BI

• Package / Case: FPBGA-180
• Maximum Operating Temperature: + 125 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 3.3 V
• Lead Free Status / Rohs Status: No RoHS Version Available

Direct Data Transfer Mode
4.2.1.3
Memory-Mapped PCI 9030 Local address spaces can
be selectively programmed to enable a Local Bus
prefetch (enabled by default in LASxBRD[5:3]). A
Prefetch Counter for each space controls the number
of prefetches to perform in conjunction with each PCI
Target read. When the Prefetch Counter is enabled
(LASxBRD[5]=1), the Prefetch Count (LASxBRD[4:3])
can be set to 0 (disabling prefetch), or to 4, 8 or 16
Lwords (independent of Local Bus width). If the
Prefetch Counter is disabled (LASxBRD[5]=0), the
PCI 9030 performs continuous prefetches.
When a PCI Target read is performed and a Local Bus
prefetch is enabled for the Local Address space, the
PCI 9030 fetches the requested data and continues to
read data from sequential addresses (anticipating the
PCI Master eventually consuming the additional data).
When the PCI 9030 prefetches, if the Prefetch
Counter is enabled, the PCI 9030 stops reading from
the Local Bus read after reaching the Prefetch Count
limit. In Continuous Prefetch mode, if PCI Target Read
Ahead mode is disabled (CNTRL[16]=0) (refer to
Section 4.2.1.4), the PCI 9030 prefetches as long as
space is available in its FIFO, and stops prefetching a
few PCI clocks after the PCI Master completes its
read. If both Continuous Prefetch and PCI Target
Read Ahead modes are enabled,
continues to prefetch until the Read FIFO is full. If
prefetch is disabled (LASxBRD[5:3]=100), or the
address space is mapped as I/O, the PCI 9030 stops
after one Read transfer.
Local prefetch must be enabled if PCI Burst reads and
Read Ahead mode are utilized.
Refer to Section 2.1.1.4 regarding mapping of
PCI 9030 address spaces into an upstream bridge’s
Prefetchable Base and Limit registers.
4.2.1.4
The PCI 9030 also supports PCI Target Read Ahead
mode (CNTRL[16]), where prefetched data can be
read from the PCI 9030 internal FIFO instead of the
Local Bus. The address must be subsequent to the
previous address and 32-bit aligned (next address =
current address + 4). The PCI Target Read Ahead
mode functions can be used with or without PCI
Target Delayed Read mode. (Refer to Figure 4-2.)
PCI 9030 Data Book Version 1.4
© 2002 PLX Technology, Inc. All rights reserved.
Local Bus Prefetch
PCI Target Read Ahead Mode
the PCI 9030
Read Ahead mode requires that Prefetch be enabled
in the LASxBRD and/or EROMBRD registers for the
Memory-Mapped spaces that use Read Ahead mode.
The PCI 9030 flushes its Read FIFO for each I/O-
Mapped access.
Figure 4-2. PCI Target Read Ahead Mode
Note:
4.2.1.5
The PCI 9030 supports PCI Target Delayed Write
mode
accumulates in the PCI Target Write FIFO before the
PCI 9030 requests a Write transaction (ADS# and/or
ALE assertion) to be performed on the Local Bus. PCI
Target Delayed Write mode is programmable to delay
the ADS# and ALE assertion for the amount of Local
clocks selected in CNTRL[11:10]. This feature is
useful for gaining higher throughput during PCI Target
Write Burst transactions for conditions in which the
PCI clock frequency is slower than the Local clock
frequency.
4.2.1.6
The PCI 9030 supports PCI Target Local Bus
READY# Timeout mode transactions, where the
PCI 9030 asserts an internal READY# signal to
recover from stalling the Local and PCI Buses. The
PCI Target Local Bus READY# Timeout mode
transaction is programmable to select the amount of
Local clocks before READY# times out (CNTRL[9:8]).
If a Local Target stalls with a READY# assertion
PCI Bus Master Read
“Sequential Address”
PCI Read request
PCI Bus
The figure represents a sequence of Bus cycles.
returns with
transactions,
Read data
Read data
PCI Target Delayed Write Mode
READY# Timeout Mode
PCI Target Local Bus
PCI Target (Direct Slave) Operation
without reading again
Read Ahead mode
from the Local Bus
Internal Registers
Prefetched data is
PCI 9030
PCI 9030 returns
immediately from
prefetched data
internal FIFO
internal FIFO
stored in the
PCI Target
where
is set in
posted
PCI 9030 prefetches
more data from
Local memory
PCI 9030 prefetches
more data if FIFO
space is available
PCI 9030 prefetches
data from
Local Bus device
Write
Local Bus
Section 4
data
4-3