PCI9030-AA60BI PLX Technology, PCI9030-AA60BI Datasheet - Page 136

• Manufacturer Part Number: PCI9030-AA60BI
• Description: Peripheral Drivers & Components (PCIs) 32-bit 33MHz PCI v.2.2-compliant
• Manufacturer: PLX Technology

Specifications of PCI9030-AA60BI

• Package / Case: FPBGA-180
• Maximum Operating Temperature: + 125 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 3.3 V
• Lead Free Status / Rohs Status: No RoHS Version Available

Section 10
Registers
Register 10-48. (LAS0BRD; 28h) Local Address Space 0 Bus Region Descriptor (Continued)
10-22
27:26
29:28
31:30
Bit
24
25
Byte Ordering. Value of 1 indicates Big Endian. Value of 0 indicates
Little Endian.
Big Endian Byte Lane Mode. Writing 1 specifies that in Big Endian mode,
use byte lanes [31:16] for a 16-bit Local Bus and byte lanes [31:24] for an
8-bit Local Bus. Writing 0 specifies that in Big Endian mode, use byte lanes
[15:0] for a 16-bit Local Bus and byte lanes [7:0] for an 8-bit Local Bus.
Read Strobe Delay. Number of clocks from beginning of cycle until RD#
strobe is asserted (0-3). Value must be
Write Strobe Delay. Number of clocks from beginning of cycle until WR#
strobe is asserted (0-3). Value must be
Write Cycle Hold. Number of clocks from WR# de-assertion until end of cycle
(0-3). Data (LAD/LD[31:0]) remains valid, and BLAST# remains asserted,
during Write Cycle Hold bus cycles.
Description
NRAD for RD# to be asserted.
NWAD for WR# to be asserted.
© 2002 PLX Technology, Inc. All rights reserved.
Read
Yes
Yes
Yes
Yes
Yes
Local Configuration Registers
PCI 9030 Data Book Version 1.4
Write
Yes
Yes
Yes
Yes
Yes
Value after
Reset
00
00
00
0
0