EP2AGX65DF29C6N Altera, EP2AGX65DF29C6N Datasheet - Page 90
EP2AGX65DF29C6N
Manufacturer Part Number
EP2AGX65DF29C6N
Description
IC ARRIA II GX FPGA 65K 780FBGA
Manufacturer
Altera
Series
Arria II GXr
Datasheets
1.EP2AGX45CU17C6N.pdf
(96 pages)
2.EP2AGX45CU17C6N.pdf
(14 pages)
3.EP2AGX45CU17C6N.pdf
(692 pages)
4.EP2AGX45CU17C6N.pdf
(10 pages)
5.EP2AGX45CU17C6N.pdf
(88 pages)
6.EP2AGX65DF29C6N.pdf
(306 pages)
Specifications of EP2AGX65DF29C6N
Number Of Logic Elements/cells
60214
Number Of Labs/clbs
2530
Total Ram Bits
5246
Number Of I /o
364
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
780-FBGA
Family Name
Arria® II GX
Number Of Logic Blocks/elements
63250
# I/os (max)
364
Frequency (max)
400MHz
Operating Supply Voltage (typ)
900mV
Logic Cells
63250
Ram Bits
5557452.8
Operating Supply Voltage (min)
0.87V
Operating Supply Voltage (max)
0.93V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
780
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP2AGX65DF29C6N
Manufacturer:
ST
Quantity:
12 000
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4–30
DSP Block Control Signals
Table 4–9. DSP Block Dynamic Signals for DSP Block (Part 1 of 2)
Arria II GX Device Handbook, Volume 1
DSP Block Dynamic Signals per Half-DSP Block
signa
signb
output_round
chainout_round
output_saturate
Signal Name
You can use the rounding and saturation function as described in regular supported
multiplication operations shown in
type operations, the following convention is used.
The functionality of the round logic unit is in the format of:
Result = RND[
Likewise, the functionality of the saturation logic unit is in the format of:
Result = SAT[
If both the round and saturation logic units are used for an accumulation type of
operation, the format is:
Result = SAT[RND[
The Arria II GX DSP block is configured using a set of static and dynamic signals. At
run time, you can configure the DSP block dynamic signals to toggled or not.
Table 4–9
Signed/unsigned control for all multipliers and adders.
signa for “multiplicand” input bus to dataa[17:0] each
multiplier.
signb for “multiplier” input bus datab[17:0] to each multiplier.
■
■
■
■
Round control for first stage round/saturation block.
■
■
Round control for second stage round/saturation block.
■
■
Saturation control for first stage round/saturation block for Q-format
multiply. If both rounding and saturation is enabled, saturation is done
on the rounded result.
■
■
shows a list of dynamic signals for the DSP block.
signa = 1, signb = 1 for signed-signed multiplication
signa = 1, signb = 0 for signed-unsigned multiplication
signa = 0, signb = 1 for unsigned-signed multiplication
signa = 0, signb = 0 for unsigned-unsigned multiplication
output_round = 1 for rounding on multiply output
output_round = 0 for normal multiply output
chainout_round = 1 for rounding on multiply output
chainout_round = 0 for normal multiply output
output_saturate = 1 for saturation support
output_saturate = 0 for no saturation support
(A × B)], when used for an accumulation type of operation.
(A × B)], when used for an accumulation type of operation.
(A × B)]]
Function
Table 4–2 on page
Chapter 4: DSP Blocks in Arria II GX Devices
4–5. However, for accumulation
© July 2010 Altera Corporation
Operational Mode Descriptions
Count
2
1
1
1
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