EP2AGX65DF29C6N Altera, EP2AGX65DF29C6N Datasheet - Page 98
EP2AGX65DF29C6N
Manufacturer Part Number
EP2AGX65DF29C6N
Description
IC ARRIA II GX FPGA 65K 780FBGA
Manufacturer
Altera
Series
Arria II GXr
Datasheets
1.EP2AGX45CU17C6N.pdf
(96 pages)
2.EP2AGX45CU17C6N.pdf
(14 pages)
3.EP2AGX45CU17C6N.pdf
(692 pages)
4.EP2AGX45CU17C6N.pdf
(10 pages)
5.EP2AGX45CU17C6N.pdf
(88 pages)
6.EP2AGX65DF29C6N.pdf
(306 pages)
Specifications of EP2AGX65DF29C6N
Number Of Logic Elements/cells
60214
Number Of Labs/clbs
2530
Total Ram Bits
5246
Number Of I /o
364
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
780-FBGA
Family Name
Arria® II GX
Number Of Logic Blocks/elements
63250
# I/os (max)
364
Frequency (max)
400MHz
Operating Supply Voltage (typ)
900mV
Logic Cells
63250
Ram Bits
5557452.8
Operating Supply Voltage (min)
0.87V
Operating Supply Voltage (max)
0.93V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
780
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP2AGX65DF29C6N
Manufacturer:
ST
Quantity:
12 000
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5–6
Table 5–3. Clock Input Pin Connectivity to RCLK Networks
Clock Input Connections to PLLs
Table 5–4. Arria II GX Device PLLs and PLL Clock Pin Drivers
Clock Output Connections
Arria II GX Device Handbook, Volume 1
RCLK [12, 14, 16, 18, 20, 22]
RCLK [13, 15, 17, 19, 21, 23]
RCLK [24..35]
RCLK [36, 38, 40, 42, 44, 46]
RCLK [37, 39, 41, 43, 45, 47]
CLK[4..7]
CLK[8..11]
CLK[12..15]
Note to
(1) PLL_5 and PLL_6 are connected directly to CLK[8..11]. PLL_1, PLL_2, PLL_3 and PLL_4 are driven by the clock input pins
through a 4:1 multiplexer.
Dedicated Clock Input Pin (CLK pins)
Table
5–4:
Clock Resource
Table 5–3
Arria II GX devices. A given clock input pin can drive two adjacent RCLK networks to
create a dual-RCLK network.
Table 5–4
PLLs in Arria II GX devices can drive up to 24 RCLK networks and 8 GCLK networks.
For Arria II GX PLL connectivity to GCLK networks, refer to
Quartus
networks.
Table 5–5
Table 5–5. Arria II GX PLL Connectivity to GCLKs
GCLK[0..3]
GCLK[4..7]
GCLK[8..11]
GCLK[12..15]
®
Clock Network
II software automatically assigns PLL clock outputs to RCLK or GCLK
lists the connectivity between the dedicated clock input pins and RCLKs in
lists dedicated clock input pin connectivity to Arria II GX PLLs.
lists how the PLL clock outputs connect to GCLK networks.
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(Note 1)
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2
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Chapter 5: Clock Networks and PLLs in Arria II GX Devices
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2
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8
PLL Number
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3
CLK (Pins)
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9
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v
PLL Number
3
10
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4
Clock Networks in Arria II GX Devices
Table
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© July 2010 Altera Corporation
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11
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5–5. The
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5
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13
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6
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15
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v
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