EP2AGX65DF29C6N Altera, EP2AGX65DF29C6N Datasheet - Page 28
EP2AGX65DF29C6N
Manufacturer Part Number
EP2AGX65DF29C6N
Description
IC ARRIA II GX FPGA 65K 780FBGA
Manufacturer
Altera
Series
Arria II GXr
Datasheets
1.EP2AGX45CU17C6N.pdf
(96 pages)
2.EP2AGX45CU17C6N.pdf
(14 pages)
3.EP2AGX45CU17C6N.pdf
(692 pages)
4.EP2AGX45CU17C6N.pdf
(10 pages)
5.EP2AGX45CU17C6N.pdf
(88 pages)
6.EP2AGX65DF29C6N.pdf
(306 pages)
Specifications of EP2AGX65DF29C6N
Number Of Logic Elements/cells
60214
Number Of Labs/clbs
2530
Total Ram Bits
5246
Number Of I /o
364
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
780-FBGA
Family Name
Arria® II GX
Number Of Logic Blocks/elements
63250
# I/os (max)
364
Frequency (max)
400MHz
Operating Supply Voltage (typ)
900mV
Logic Cells
63250
Ram Bits
5557452.8
Operating Supply Voltage (min)
0.87V
Operating Supply Voltage (max)
0.93V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
780
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP2AGX65DF29C6N
Manufacturer:
ST
Quantity:
12 000
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2–2
LAB Interconnects
Arria II GX Device Handbook, Volume 1
f
Half of the available LABs in Arria II GX devices can be used as a memory LAB
(MLAB). The MLAB supports a maximum of 640 bits of simple dual-port static
random access memory (SRAM). You can configure each ALM in an MLAB as either a
64 × 1 or 32 × 2 block, resulting in a configuration of 64 × 10 or 32 × 20 simple
dual-port SRAM blocks. MLAB and LAB blocks always coexist as pairs in all
Arria II GX device families. MLAB is a superset of the LAB and includes all LAB
features.
MLAB is described in detail in the
volume 1 of the Arria II GX Device Handbook.
Figure 2–2. Arria II GX LAB and MLAB Structure
Note to
(1) You can use an MLAB ALM as a regular LAB ALM or configure it as a dual-port SRAM, as shown.
The LAB local interconnect is used to drive ALMs in the same LAB. Each LAB can
drive 30 ALMs through fast local and direct link interconnects. Ten ALMs are in any
given LAB and ten ALMs are in each of the adjacent LABs.
Figure
Figure 2–2
2–2:
shows an overview of LAB and MLAB topology.
Simple dual port SRAM
Simple dual port SRAM
Simple dual port SRAM
Simple dual port SRAM
Simple dual port SRAM
Simple dual port SRAM
Simple dual port SRAM
Simple dual port SRAM
Simple dual port SRAM
Simple dual port SRAM
LAB Control Block
LUT-based-64 x 1
LUT-based-64 x 1
LUT-based-64 x 1
LUT-based-64 x 1
LUT-based-64 x 1
LUT-based-64 x 1
LUT-based-64 x 1
LUT-based-64 x 1
LUT-based-64 x 1
LUT-based-64 x 1
Chapter 2: Logic Array Blocks and Adaptive Logic Modules in Arria II GX Devices
MLAB
Memory Blocks in Arria II GX Devices
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
LAB Control Block
LAB
ALM
ALM
ALM
ALM
ALM
ALM
ALM
ALM
ALM
ALM
© June 2009 Altera Corporation
chapter in
Logic Array Blocks
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