EP2AGX65DF29C6N Altera, EP2AGX65DF29C6N Datasheet - Page 229

• Manufacturer Part Number: EP2AGX65DF29C6N
• Description: IC ARRIA II GX FPGA 65K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX65DF29C6N

• Number Of Logic Elements/cells: 60214
• Number Of Labs/clbs: 2530
• Total Ram Bits: 5246
• Number Of I /o: 364
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 63250
• # I/os (max): 364
• Frequency (max): 400MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 63250
• Ram Bits: 5557452.8
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

Chapter 9: Configuration, Design Security, and Remote System Upgrades in Arria II GX Devices
Fast Passive Parallel Configuration
© July 2010
Altera Corporation
1
Figure 9–1
device and a MAX II device for single device configuration.
Figure 9–1. Single Device FPP Configuration Using an External Host
Notes to
(1) Connect the resistor to a supply that provides an acceptable input signal for the Arria II GX device. V
(2) You can leave the nCEO pin unconnected or used as a user I/O pin when it does not feed the nCE pin of the other
(3) The MSEL pin settings vary for different configuration voltage standards and POR delay. To connect MSEL[3..0],
Arria II GX devices receive configuration data on the DATA[7..0] pins and the clock
is received on the DCLK pin. Data is latched into the device on the rising edge of DCLK.
If you are using the Arria II GX decompression and/or design security features,
configuration data is latched on the rising edge of every fourth DCLK cycle. After the
configuration data is latched in, it is processed during the following three DCLK
cycles. Therefore, you can only stop DCLK after three clock cycles after the last data is
latched into the Arria II GX devices.
enough to meet the V
power up the configuration system's I/Os with V
device.
refer to
Figure
Table 9–2 on page
shows the configuration interface connections between the Arria II GX
9–1:
(MAX II Device or
Microprocessor)
External Host
ADDR DATA[7..0]
IH
specification of the I/O on both the device and external host. Altera recommends that you
Memory
9–7.
10 kΩ
V
CCIO
CCIO
for I/O bank 3C.
(1)
V
CCIO
10 kΩ
GND
(1)
CONF_DONE
nSTATUS
nCE
nCONFIG
DCLK
DATA[7..0]
Arria II GX Device
Arria II GX Device Handbook, Volume 1
MSEL[3..0]
nCEO
N.C. (2)
CCIO
(3)
must be high
9–9