EP2AGX65DF29C6N Altera, EP2AGX65DF29C6N Datasheet - Page 123

• Manufacturer Part Number: EP2AGX65DF29C6N
• Description: IC ARRIA II GX FPGA 65K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX65DF29C6N

• Number Of Logic Elements/cells: 60214
• Number Of Labs/clbs: 2530
• Total Ram Bits: 5246
• Number Of I /o: 364
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 63250
• # I/os (max): 364
• Frequency (max): 400MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 63250
• Ram Bits: 5557452.8
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

Chapter 5: Clock Networks and PLLs in Arria II GX Devices
PLLs in Arria II GX Devices
Figure 5–24. PLL Reconfiguration Scan Chain
Notes to
(1) The Arria II GX PLLs support
(2) i = 6
(3) This figure shows the corresponding scan register for the K counter in between the scan registers for the charge pump and loop filter. The
© July 2010
scanclkena
configupdate
scandataout
K counter is physically located after the VCO.
scandone
scandata
Figure
inclk
Altera Corporation
scanclk
f
5–24:
1
PLL Reconfiguration Hardware Implementation
The following PLL components are reconfigurable in real time:
■
■
■
■
■
Figure 5–24
shifting their new settings into a serial shift-register chain or scan chain. Serial data is
input to the scan chain with the scandataport and shift registers are clocked by
scanclk. The maximum scanclk frequency is 100 MHz. Serial data is shifted
through the scan chain as long as the scanclkena signal stays asserted. After the last
bit of data is clocked, asserting the configupdate signal for at least one scanclk
clock cycle causes the PLL configuration bits to be synchronously updated with the
data in the scan registers.
For more information about the PLL reconfiguration port signals, refer to the
Locked-Loops Reconfiguration (ALTPLL_RECONFIG) Megafunction User
The counter settings are updated synchronously to the clock frequency of the
individual counters. Therefore, all counters are not simultaneously updated.
from m counter
from n counter
/Ci (2)
Pre-scale counter (n)
Feedback counter (m)
Post-scale output counters (C0 to C6)
Post VCO divider (K)
Dynamically adjust the charge-pump current (Icp) and loop-filter components
(R and C) to facilitate reconfiguration of the PLL bandwidth
C0
to
C6
/Ci-1
counters.
shows how you can dynamically adjust the PLL counter settings by
PFD
/C2
LF/K/CP (3)
/C1
/C0
VCO
Arria II GX Device Handbook, Volume 1
/m
Guide.
/n
Phase
5–31