EP2AGX65DF29C6N Altera, EP2AGX65DF29C6N Datasheet - Page 140
EP2AGX65DF29C6N
Manufacturer Part Number
EP2AGX65DF29C6N
Description
IC ARRIA II GX FPGA 65K 780FBGA
Manufacturer
Altera
Series
Arria II GXr
Datasheets
1.EP2AGX45CU17C6N.pdf
(96 pages)
2.EP2AGX45CU17C6N.pdf
(14 pages)
3.EP2AGX45CU17C6N.pdf
(692 pages)
4.EP2AGX45CU17C6N.pdf
(10 pages)
5.EP2AGX45CU17C6N.pdf
(88 pages)
6.EP2AGX65DF29C6N.pdf
(306 pages)
Specifications of EP2AGX65DF29C6N
Number Of Logic Elements/cells
60214
Number Of Labs/clbs
2530
Total Ram Bits
5246
Number Of I /o
364
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
780-FBGA
Family Name
Arria® II GX
Number Of Logic Blocks/elements
63250
# I/os (max)
364
Frequency (max)
400MHz
Operating Supply Voltage (typ)
900mV
Logic Cells
63250
Ram Bits
5557452.8
Operating Supply Voltage (min)
0.87V
Operating Supply Voltage (max)
0.93V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
780
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP2AGX65DF29C6N
Manufacturer:
ST
Quantity:
12 000
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6–6
Figure 6–2. Arria II GX IOE Structure
3.3-V I/O Interface
Arria II GX Device Handbook, Volume 1
Write
To
Core
To
Core
Data
form
Core
Read
Data
to
Core
CQn
OE
from
Core
DQS
clkin
f
Figure 6–2
For more information about I/O registers and how they are used for memory
applications, refer to the
Arria II GX I/O buffers are fully compatible with 3.3-V I/O standards. You can use
them as transmitters or receivers in your system. The output high voltage (V
output low voltage (V
meet the 3.3-V I/O standard specifications defined by EIA/JEDEC Standard JESD8-B
with margin when the Arria II GX V
To ensure device reliability and proper operation when interfacing with a 3.3-V I/O
system with Arria II GX devices, it is important to ensure that the absolute maximum
ratings are not violated. Altera recommends performing IBIS simulation to determine
that the overshoot and undershoot voltages are in the guidelines. There are several
techniques that you can use to limit overshoot and undershoot voltages, though none
are required.
to internal Cells
Input Pin Delay
Synchronization
Registers
Input Register Delay
shows the Arria II GX IOE structure.
DQS Bus
to
Output Register
Output Register
OE Register
OE Register
D
D
D
D
PRN
PRN
PRN
PRN
Q
Q
Q
Q
OL
), input high voltage (V
External Memory Interfaces in Arria II GX Devices
to Input Register
Input Pin Delay
Input Register
Input Register
D
D
PRN
PRN
Q
Q
CCIO
Output Pin
Delay
Output Enable
Input Register
voltage is powered by 3.3 V or 3.0 V.
Programmable
D
Pin Delay
Strength and
Slew Rate
PRN
Current
Control
Q
Open Drain
IH
), and input low voltage (V
Output Buffer
Chapter 6: I/O Features in Arria II GX Devices
Input Buffer
V
CCIO
© July 2010 Altera Corporation
V
CCIO
Pull-Up Resistor
Programmable
Termination
Calobration
From OCT
On-Chip
Arria II GX I/O Structure
Bus-Hold
Block
Circuit
chapter.
IL
OH
) levels
),
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