EP2AGX65DF29C6N Altera, EP2AGX65DF29C6N Datasheet - Page 50

• Manufacturer Part Number: EP2AGX65DF29C6N
• Description: IC ARRIA II GX FPGA 65K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX65DF29C6N

• Number Of Logic Elements/cells: 60214
• Number Of Labs/clbs: 2530
• Total Ram Bits: 5246
• Number Of I /o: 364
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 63250
• # I/os (max): 364
• Frequency (max): 400MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 63250
• Ram Bits: 5557452.8
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

3–10
Simple Dual-Port Mode
Table 3–4. Arria II GX M9K Block Mixed-Width Configurations
Arria II GX Device Handbook, Volume 1
8K×1
4K×2
2K×4
1K×8
512×16
256×32
1K×9
512×18
256×36
Read Port
All memory blocks support simple dual-port mode. Simple dual-port mode allows
you to perform one-read and one-write operation to different locations at the same
time.
Figure 3–11. Arria II GX Simple Dual-Port Memory
Note to
(1) Simple dual-port RAM supports input and output clock mode in addition to the read and write clock mode shown.
Simple dual-port mode supports different read and write data widths (mixed width
support).
dual-port mode. MLABs do not have native support for mixed width operations. The
Quartus II software can implement mixed width memories in MLABs with more than
one MLAB.
In simple dual-port mode, M9K blocks support separate write-enable and read-enable
signals. Read-during-write operations to the same address can either output a don’t
care value or old data.
MLABs only support a write-enable signal. Read-during-write behavior for the
MLABs can be either don’t care or old data. The available choices depend on the
configuration of the MLAB.
Figure 3–12
dual-port mode with unregistered outputs for M9K. Registering the M9K’s outputs
would simply delay the q output by one clock cycle.
8K×1
v
v
v
v
v
v
—
—
—
Figure 3–11
Figure
Table 3–4
4K×2
v
v
v
v
v
v
—
—
—
3–11:
shows timing waveforms for read and write operations in simple
shows a simple dual-port configuration.
2K×4
lists the mixed width configurations for the M9K blocks in simple
v
v
v
v
v
v
—
—
—
1K×8
data[ ]
wraddress[ ]
wren
byteena[]
wr_addressstall
wrclock
wrclocken
aclr
v
v
v
v
v
v
—
—
—
512×16
Write Port
v
v
v
v
v
v
—
—
—
(Note 1)
rd_addressstall
256×32
v
v
v
v
v
v
—
—
—
rdaddress[ ]
Chapter 3: Memory Blocks in Arria II GX Devices
rdclocken
rdclock
rden
q[ ]
© November 2009 Altera Corporation
1K×9
—
—
—
—
—
—
v
v
v
512×18
—
—
—
—
—
—
v
v
v
Memory Modes
256×36
—
—
—
—
—
—
v
v
v