EP2AGX65DF29C6N Altera, EP2AGX65DF29C6N Datasheet - Page 155

• Manufacturer Part Number: EP2AGX65DF29C6N
• Description: IC ARRIA II GX FPGA 65K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX65DF29C6N

• Number Of Logic Elements/cells: 60214
• Number Of Labs/clbs: 2530
• Total Ram Bits: 5246
• Number Of I /o: 364
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 63250
• # I/os (max): 364
• Frequency (max): 400MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 63250
• Ram Bits: 5557452.8
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

Chapter 6: I/O Features in Arria II GX Devices
Arria II GX Design Considerations
Arria II GX Design Considerations
I/O Termination
© July 2010 Altera Corporation
f
1
A resistor network is required to attenuate the LVDS output voltage swing to meet
mini-LVDS specifications. You can modify the three-resistor network values to reduce
power or improve the noise margin. The resistor values chosen should satisfy the
equation shown in
Equation 6–2.
To validate that custom resistor values meet the RSDS requirements, Altera
recommends performing additional simulations with IBIS models.
For more information about the mini-LVDS I/O standard, see the mini-LVDS
Specification from the Texas Instruments website at www.ti.com.
While Arria II GX devices feature various I/O capabilities for high-performance and
high-speed system designs, the following items require attention to ensure the success
of these designs:
■
■
■
This section describes I/O termination requirements for single-ended and differential
I/O standards.
Single-Ended I/O Standards
Although single-ended, non-voltage-referenced I/O standards do not require
termination, impedance matching is necessary to reduce reflections and improve
signal integrity.
Voltage-referenced I/O standards require both an input reference voltage (V
termination voltage (V
termination voltage of the transmitting device. Each voltage-referenced I/O standard
requires a specific termination setup. For example, a proper resistive signal
termination scheme is critical in SSTL2 standards to produce a reliable DDR memory
system with a superior noise margin.
“I/O Termination” on page 6–21
“I/O Bank Restrictions” on page 6–22
“I/O Placement Guidelines” on page 6–23
Equation
TT
). The reference voltage of the receiving device tracks the
6–2.
R
R
S x
S +
R
2
R
P
2
P
= 50 Ω
Arria II GX Device Handbook, Volume 1
REF
) and a
6–21