EP2AGX65DF29C6N Altera, EP2AGX65DF29C6N Datasheet - Page 230

• Manufacturer Part Number: EP2AGX65DF29C6N
• Description: IC ARRIA II GX FPGA 65K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX65DF29C6N

• Number Of Logic Elements/cells: 60214
• Number Of Labs/clbs: 2530
• Total Ram Bits: 5246
• Number Of I /o: 364
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 63250
• # I/os (max): 364
• Frequency (max): 400MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 63250
• Ram Bits: 5557452.8
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

9–10
Figure 9–2. Multi-Device FPP Configuration Using an External Host
Notes to
(1) Connect the pull-up resistor to a supply that provides an acceptable input signal for all Arria II GX devices in the chain. V
(2) The MSEL pin settings vary for different configuration voltage standards and POR delay. To connect MSEL[3..0], refer to
Arria II GX Device Handbook, Volume 1
to meet the V
I/Os with V
page
Figure
9–7.
(MAX II Device or
Microprocessor)
External Host
ADDR DATA[7..0]
CCIO
9–2:
IH
specification of the I/O standard on the device and external host. Altera recommends that you power up the configuration system's
for I/O bank 3C.
Memory
Figure 9–2
circuit is similar to the FPP configuration circuit for a single device, except the
Arria II GX devices are cascaded for multi-device configuration.
After the first device completes configuration in a multi-device configuration chain,
its nCEO pin drives low to activate the nCE pin of the second device, which prompts
the second device to begin configuration. The second device in the chain begins
configuration in one clock cycle; therefore, the transfer of data destinations is
transparent to the MAX II device or microprocessor. All other configuration pins
(nCONFIG, nSTATUS, DCLK, DATA[7..0], and CONF_DONE) are connected to every
device in the chain. The configuration signals may require buffering to ensure signal
integrity and prevent clock skew problems. Ensure that the DCLK and DATA lines are
buffered for every fourth device. Because all device CONF_DONE pins are tied together,
all devices initialize and enter user mode at the same time.
All nSTATUS and CONF_DONE pins are tied together and if any device detects an error,
configuration stops for the entire chain and you must reconfigure the entire chain. For
example, if the first device flags an error on nSTATUS, it resets the chain by pulling its
nSTATUS pin low. This behavior is similar to a single device detecting an error.
If a system has multiple devices that contain the same configuration data, tie all
device nCE inputs to GND and leave the nCEO pins floating. All other configuration
pins (nCONFIG, nSTATUS, DCLK, DATA[7..0], and CONF_DONE) are connected to
every device in the chain. Configuration signals may require buffering to ensure
signal integrity and prevent clock skew problems. Ensure that the DCLK and DATA
lines are buffered for every fourth device. Devices must be the same density and
package. All devices start and complete configuration at the same time.
V
10 kΩ
CCIO
shows how to configure multiple devices using a MAX II device. This
(1)
V
Chapter 9: Configuration, Design Security, and Remote System Upgrades in Arria II GX Devices
CCIO
10 kΩ
(1)
GND
CONF_DONE
nSTATUS
nCE
DATA[7..0]
nCONFIG
DCLK
Arria II GX Device 1
MSEL[3..0]
nCEO
(2)
V
CCIO
10 kΩ
(1)
Fast Passive Parallel Configuration
© July 2010 Altera Corporation
Arria II GX Device 2
CONF_DONE
nSTATUS
nCE
DATA[7..0]
nCONFIG
DCLK
CCIO
MSEL[3..0]
must be high enough
Table 9–2 on
nCEO
N.C.
(2)