EP2AGX65DF29C6N Altera, EP2AGX65DF29C6N Datasheet - Page 43

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EP2AGX65DF29C6N

Manufacturer Part Number
EP2AGX65DF29C6N
Description
IC ARRIA II GX FPGA 65K 780FBGA
Manufacturer
Altera
Series
Arria II GXr

Specifications of EP2AGX65DF29C6N

Number Of Logic Elements/cells
60214
Number Of Labs/clbs
2530
Total Ram Bits
5246
Number Of I /o
364
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
780-FBGA
Family Name
Arria® II GX
Number Of Logic Blocks/elements
63250
# I/os (max)
364
Frequency (max)
400MHz
Operating Supply Voltage (typ)
900mV
Logic Cells
63250
Ram Bits
5557452.8
Operating Supply Voltage (min)
0.87V
Operating Supply Voltage (max)
0.93V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
780
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant

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Chapter 3: Memory Blocks in Arria II GX Devices
Memory Features
Byte Enable Support
Figure 3–1. Arria II GX Byte Enable Functional Waveform for M9K
© November 2009
current data: q (asynch)
don't care: q (asynch)
contents at a0
contents at a1
contents at a2
address
byteena
inclock
wren
data
Altera Corporation
XXXX
XX
All memory blocks support byte enables that mask the input data so that only specific
bytes of data are written. The unwritten bytes retain the previous written value. The
write enable (wren) signals, along with the byte enable (byteena) signals, control the
RAM blocks’ write operations.
The default value for the byte enable signals is high (enabled), in which case writing is
controlled only by the write enable signals. The byte enable registers have no clear
port. When using parity bits on the M9K blocks, the byte enable controls all nine bits
(eight bits of data plus one parity bit). When using parity bits on the MLAB, the
byte-enable controls all 10 bits in the widest mode.
Byte enables operate in a one-hot fashion, with the LSB of the byteena signal
corresponding to the LSB of the data bus. For example, if you use a RAM block in ×18
mode, byteena = 01, data[8..0] is enabled and data[17..9] is disabled.
Similarly, if byteena = 11, both data[8..0] and data[17..9] are enabled. Byte
enables are active high.
Figure 3–1
control the operations of the M9K.
When a byte-enable bit is de-asserted during a write cycle, the corresponding data
byte output can appear as either a “don’t care” value or the current data at that
location. The output value for the masked byte is controllable using the Quartus II
software. When a byte-enable bit is asserted during a write cycle, the corresponding
data byte output also depends on the setting chosen in the Quartus II software.
an
FFFF
doutn
doutn
FFFF
shows how the write enable (wren) and byte enable (byteena) signals
10
a0
FFFF
ABXX
ABFF
ABCD
01
a1
XXCD
FFCD
11
a2
ABCD
ABCD
ABFF
a0
FFCD
ABFF
ABFF
Arria II GX Device Handbook, Volume 1
ABCD
a1
XXXX
XX
FFCD
FFCD
a2
ABCD
ABCD
3–3

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