EP2AGX65DF29C6N Altera, EP2AGX65DF29C6N Datasheet - Page 151
EP2AGX65DF29C6N
Manufacturer Part Number
EP2AGX65DF29C6N
Description
IC ARRIA II GX FPGA 65K 780FBGA
Manufacturer
Altera
Series
Arria II GXr
Datasheets
1.EP2AGX45CU17C6N.pdf
(96 pages)
2.EP2AGX45CU17C6N.pdf
(14 pages)
3.EP2AGX45CU17C6N.pdf
(692 pages)
4.EP2AGX45CU17C6N.pdf
(10 pages)
5.EP2AGX45CU17C6N.pdf
(88 pages)
6.EP2AGX65DF29C6N.pdf
(306 pages)
Specifications of EP2AGX65DF29C6N
Number Of Logic Elements/cells
60214
Number Of Labs/clbs
2530
Total Ram Bits
5246
Number Of I /o
364
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
780-FBGA
Family Name
Arria® II GX
Number Of Logic Blocks/elements
63250
# I/os (max)
364
Frequency (max)
400MHz
Operating Supply Voltage (typ)
900mV
Logic Cells
63250
Ram Bits
5557452.8
Operating Supply Voltage (min)
0.87V
Operating Supply Voltage (max)
0.93V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
780
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP2AGX65DF29C6N
Manufacturer:
ST
Quantity:
12 000
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Chapter 6: I/O Features in Arria II GX Devices
Arria II GX Termination Schemes for I/O Standards
Figure 6–9. Arria II GX Differential HSTL I/O Standard Termination
© July 2010 Altera Corporation
Termination
External
On-Board
Termination
Series
OCT
Arria II GX
Arria II GX
Series OCT
Transmitter
Transmitter
HSTL Class I
50 Ω
Figure 6–9
Arria II GX devices.
LVDS
The LVDS I/O standard is a differential high-speed, low-voltage swing, low-power,
general-purpose I/O interface standard. In Arria II GX devices, the LVDS I/O
standard requires a 2.5-V V
LVDS requires a 100- termination resistor between the two signals at the input
buffer. Arria II GX devices provide an optional 100- differential termination resistor
in the device with R
700 Mbps.
HSTL Class I
Z
Z
50 Ω
50 Ω
0
0
= 50 Ω
= 50 Ω
50 Ω
shows the details of differential HSTL I/O standard termination on
V TT V TT
V TT
V TT
50 Ω
50 Ω
50 Ω
D
OCT. The external-resistor topology is for a data rate of up to
Receiver
Receiver
CCIO
level. The LVDS input buffer requires 2.5-V V
Arria II GX
Series OCT
Arria II GX
Transmitter
HSTL Class II
Transmitter
25 Ω
50 Ω
V TT V TT
V TT
V TT
50 Ω
50 Ω
Z
Z
0
0
50 Ω
= 50 Ω
= 50 Ω
HSTL Class II
50 Ω
50 Ω
Arria II GX Device Handbook, Volume 1
50 Ω
V TT
V TT
V TT V TT
50 Ω
50 Ω
50 Ω
Receiver
Receiver
CCPD
.
6–17
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