EP2AGX65DF29C6N Altera, EP2AGX65DF29C6N Datasheet - Page 38

• Manufacturer Part Number: EP2AGX65DF29C6N
• Description: IC ARRIA II GX FPGA 65K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX65DF29C6N

• Number Of Logic Elements/cells: 60214
• Number Of Labs/clbs: 2530
• Total Ram Bits: 5246
• Number Of I /o: 364
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 63250
• # I/os (max): 364
• Frequency (max): 400MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 63250
• Ram Bits: 5557452.8
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

2–12
Register Chain
Arria II GX Device Handbook, Volume 1
1
In addition to general routing outputs, the ALMs in any given LAB have register
chain outputs. This allows registers in the same LAB to be cascaded together. The
register chain interconnect allows a LAB to use LUTs for a single combinational
function and the registers to be used for an unrelated shift register implementation.
These resources speed up connections between ALMs while saving local interconnect
resources (refer to
advantage of these resources to improve utilization and performance.
Figure 2–12. Register Chain in an LAB
Note to
(1) You can use the combinational or adder logic to implement an unrelated, un-registered function.
For more information about register chain interconnect, refer to
on page
Figure
2–13.
2–12:
Combinational
Combinational
Logic
Logic
Figure
Chapter 2: Logic Array Blocks and Adaptive Logic Modules in Arria II GX Devices
2–12). The Quartus II Compiler automatically takes
adder0
adder1
adder0
adder1
(Note 1)
reg_chain_out
reg_chain_in
labclk
D
D
D
D
reg0
reg1
reg0
reg1
From previous ALM
in the LAB
To next ALM
in the LAB
Q
Q
Q
Q
© June 2009 Altera Corporation
“ALM Interconnects”
Adaptive Logic Modules
To general or
To general or
To general or
To general or
To general or
To general or
To general or
To general or
local routing
local routing
local routing
local routing
local routing
local routing
local routing
local routing