EP2AGX65DF29C6N Altera, EP2AGX65DF29C6N Datasheet - Page 34

• Manufacturer Part Number: EP2AGX65DF29C6N
• Description: IC ARRIA II GX FPGA 65K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX65DF29C6N

• Number Of Logic Elements/cells: 60214
• Number Of Labs/clbs: 2530
• Total Ram Bits: 5246
• Number Of I /o: 364
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 63250
• # I/os (max): 364
• Frequency (max): 400MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 63250
• Ram Bits: 5557452.8
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

2–8
Figure 2–7. Template for Supported Seven-Input Functions in Extended LUT Mode
Note to
(1) If the seven-input function is unregistered, the unused eighth input is available for register packing. The second register, reg1, is
Figure 2–8. ALM in Arithmetic Mode
Arria II GX Device Handbook, Volume 1
not available.
Figure
2–7:
datae0
datae1
datae0
dataf1
dataf0
datae1
dataf0
dataf1
datac
dataa
datab
datad
datab
dataa
datad
datac
(1)
Arithmetic Mode
Arithmetic mode is ideal for implementing adders, counters, accumulators, wide
parity functions, and comparators. The ALM in arithmetic mode uses two sets of 2
four-input LUTs along with two dedicated full adders. The dedicated adders allow
the LUTs to be available to perform pre-adder logic; therefore, each adder can add the
output of 2 four-input functions.
This input is available
for register packing.
5-Input
5-Input
LUT
LUT
4-Input
4-Input
4-Input
4-Input
LUT
LUT
LUT
LUT
Chapter 2: Logic Array Blocks and Adaptive Logic Modules in Arria II GX Devices
combout0
carry_out
carry_in
Figure 2–8
adder0
adder1
shows an ALM in arithmetic mode.
D
D
D
reg0
reg0
reg1
Q
Q
Q
To general or
To general or
To general or
To general or
To general or
To general or
local routing
local routing
local routing
local routing
local routing
local routing
© June 2009 Altera Corporation
Adaptive Logic Modules