EP2AGX65DF29C6N Altera, EP2AGX65DF29C6N Datasheet - Page 103

• Manufacturer Part Number: EP2AGX65DF29C6N
• Description: IC ARRIA II GX FPGA 65K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX65DF29C6N

• Number Of Logic Elements/cells: 60214
• Number Of Labs/clbs: 2530
• Total Ram Bits: 5246
• Number Of I /o: 364
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 63250
• # I/os (max): 364
• Frequency (max): 400MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 63250
• Ram Bits: 5557452.8
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

Chapter 5: Clock Networks and PLLs in Arria II GX Devices
Clock Networks in Arria II GX Devices
Figure 5–8. clkena Signals
Note to
(1) You can use the clkena signals to enable or disable the GCLK and RCLK networks or the PLL<#>_CLKOUT pins.
© July 2010
gate with R2 not bypassed
gate with R2 bypassed
Figure
select multiplexer
output of AND
output of AND
Altera Corporation
5–8:
output of
clkena
clock
In Arria II GX devices, the clkena signals are supported at the clock network level
instead of at the PLL output counter level. This allows you to gate off the clock even
when a PLL is not used. You can also use the clkena signals to control the dedicated
external clocks from the PLLs.
output enable. The clkena signal is synchronous to the falling edge of the clock
output.
Arria II GX devices also have an additional metastability register that aids in
asynchronous enable or disable of the GCLK and RCLK networks. You can optionally
bypass this register in the Quartus II software.
The PLL can remain locked independent of the clkena signals because the
loop-related counters are not affected. This feature is useful for applications that
require a low power or sleep mode. The clkena signal can also disable clock outputs
if the system is not tolerant of frequency over-shoot during resynchronization.
Figure 5–8
shows a waveform example for the clock
Arria II GX Device Handbook, Volume 1
5–11