EP2AGX65DF29C6N Altera, EP2AGX65DF29C6N Datasheet - Page 24

• Manufacturer Part Number: EP2AGX65DF29C6N
• Description: IC ARRIA II GX FPGA 65K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX65DF29C6N

• Number Of Logic Elements/cells: 60214
• Number Of Labs/clbs: 2530
• Total Ram Bits: 5246
• Number Of I /o: 364
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 63250
• # I/os (max): 364
• Frequency (max): 400MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 63250
• Ram Bits: 5557452.8
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

1–10
Nios II
Configuration Features
Arria II GX Device Handbook, Volume 1
f
Table 1–7
Table 1–7. External Memory Interface Maximum Performance for Arria II GX Devices—Preliminary
For more information about the external memory interfaces support, refer to the
External Memory Interfaces in Arria II GX Devices
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QDR II+/QDR II SRAM
Arria II GX devices support all variants of the NIOS
Nios II processors are supported by an array of software tools from Altera and
leading embedded partners and are used by more designers than any other
configurable processor
Configuration
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Design Security
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Remote System Upgrade
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DDR2 SDRAM
DDR3 SDRAM
Memory Type
DDR SDRAM
Supports active serial (AS), passive serial (PS), fast passive parallel (FPP), and
JTAG configuration schemes.
Supports programming file encryption using 256-bit volatile and non-volatile
security keys to protect designs from copying, reverse engineering, and
tampering in FPP configuration mode with an external host (such as a MAX
device or microprocessor), or when using the AS or PS configuration scheme
Decrypts an encrypted configuration bitstream using the AES algorithm, an
industry standard encryption algorithm that is FIPS-197 certified and requires
a 256-bit security key
Allows error-free deployment of system upgrades from a remote location
securely and reliably without an external controller
Soft logic (either the Nios II embedded processor or user logic) implementation
in the device helps download a new configuration image from a remote
location, store it in configuration memory, and direct the dedicated remote
system upgrade circuitry to start a reconfiguration cycle
Dedicated circuitry in the remote system upgrade helps to avoid system down
time by performing error detection during and after the configuration process,
recover from an error condition by reverting back to a safe configuration
image, and provides error status information
lists the preliminary external memory support.
Maximum Performance
chapter.
200 MHz
333 MHz
400 MHz
250 MHz
Chapter 1: Arria II GX Device Family Overview
®
II processor
© July 2010 Altera Corporation
Arria II GX Device Architecture
®
II