EP2AGX65DF29C6N Altera, EP2AGX65DF29C6N Datasheet - Page 289
EP2AGX65DF29C6N
Manufacturer Part Number
EP2AGX65DF29C6N
Description
IC ARRIA II GX FPGA 65K 780FBGA
Manufacturer
Altera
Series
Arria II GXr
Datasheets
1.EP2AGX45CU17C6N.pdf
(96 pages)
2.EP2AGX45CU17C6N.pdf
(14 pages)
3.EP2AGX45CU17C6N.pdf
(692 pages)
4.EP2AGX45CU17C6N.pdf
(10 pages)
5.EP2AGX45CU17C6N.pdf
(88 pages)
6.EP2AGX65DF29C6N.pdf
(306 pages)
Specifications of EP2AGX65DF29C6N
Number Of Logic Elements/cells
60214
Number Of Labs/clbs
2530
Total Ram Bits
5246
Number Of I /o
364
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
780-FBGA
Family Name
Arria® II GX
Number Of Logic Blocks/elements
63250
# I/os (max)
364
Frequency (max)
400MHz
Operating Supply Voltage (typ)
900mV
Logic Cells
63250
Ram Bits
5557452.8
Operating Supply Voltage (min)
0.87V
Operating Supply Voltage (max)
0.93V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
780
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP2AGX65DF29C6N
Manufacturer:
ST
Quantity:
12 000
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Chapter 10: SEU Mitigation in Arria II GX Devices
Error Detection Block
Error Detection Block
Table 10–4. Two Types of CRC Detection
© July 2010
■
■
■
■
■
■
This is the CRAM error checking ability (16-bit CRC)
during user mode for use by the CRC_ERROR pin.
For each frame of data, the pre-calculated 16-bit CRC
enters the CRC circuit at the end of the frame data and
determines whether there is an error or not.
If an error occurs, the search engine finds the location
of the error.
The error messages can be shifted out through the
JTAG instruction or core interface logics while the
error detection block continues running.
The JTAG interface reads out the 16-bit CRC result for
the first frame and also shifts the 16-bit CRC bits to the
16-bit CRC storage registers for test purposes.
Single error, double errors, or double errors adjacent
to each other can be deliberately introduced to
configuration memory for testing and design
verification.
Altera Corporation
1
User Mode CRC Detection
The error detection block contains the logic necessary to calculate the 16-bit CRC
signature for the configuration CRAM bits in the Arria II GX device.
The CRC circuit continues running even if an error occurs. When a soft error occurs,
the device sets the CRC_ERROR pin high. The two types of CRC detection that check
the configuration bits are shown in
The
when the device is in user mode.
“Error Detection Block”
section focuses on the first type, the 16-bit CRC only,
■
■
■
This is the 16-bit CRC that is embedded in every
configuration data frame.
During configuration, after a frame of data is loaded into the
Arria II GX device, the pre-computed CRC is shifted into the
CRC circuitry.
At the same time, the CRC value for the data frame shifted-in
is calculated. If the pre-computed CRC and calculated CRC
values do not match, nSTATUS is set low. Every data frame
has a 16-bit CRC; therefore, there are many 16-bit CRC
values for the whole configuration bitstream. Every device
has different lengths of the configuration data frame.
Table
10–4.
Configuration CRC Detection
Arria II GX Device Handbook, Volume 1
10–5
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