EP2AGX65DF29C6N Altera, EP2AGX65DF29C6N Datasheet - Page 260

• Manufacturer Part Number: EP2AGX65DF29C6N
• Description: IC ARRIA II GX FPGA 65K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX65DF29C6N

• Number Of Logic Elements/cells: 60214
• Number Of Labs/clbs: 2530
• Total Ram Bits: 5246
• Number Of I /o: 364
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 63250
• # I/os (max): 364
• Frequency (max): 400MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 63250
• Ram Bits: 5557452.8
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

9–40
Table 9–12. Optional Configuration Pins (Part 2 of 2)
Table 9–13. Dedicated JTAG Pins
Arria II GX Device Handbook, Volume 1
DEV_OE
DEV_CLRn
Pin Name
TDI
TDO
TMS
TCK
Pin Name
Mode
User
N/A
N/A
N/A
N/A
N/A if option is on.
N/A if option is on.
I/O if option is off.
I/O if option is off.
Table 9–13
during configuration to prevent accidental loading of JTAG instructions. TDI and TMS
have weak internal pull-up resistors while TCK has a weak internal pull-down resistor
(typically 25 k ). If you plan to use the SignalTap
you must connect the JTAG pins of the Arria II GX device to a JTAG header on your
board.
Pin Type
User Mode
Output
Input
Input
Input
lists the dedicated JTAG pins. JTAG pins must be kept stable before and
Serial input pin for instructions as well as test and programming data. Data is shifted on
the rising edge of TCK. The TDI pin is powered by the V
8C.
If the JTAG interface is not required on the board, you can disable the JTAG circuitry by
connecting this pin to logic high.
Serial data output pin for instructions as well as test and programming data. Data is
shifted out on the falling edge of TCK. The pin is tri-stated if data is not being shifted
out of the device. The TDO pin is powered up by the V
For recommendations about connecting a JTAG chain with multiple voltages across the
devices in the chain, refer to the
If the JTAG interface is not required on the board, you can disable the JTAG circuitry by
leaving this pin unconnected.
Input pin that provides the control signal to determine the transitions of the TAP
controller state machine. TMS is evaluated on the rising edge of TCK. Therefore, you
must set up TMS before the rising edge of TCK. Transitions in the state machine occur
on the falling edge of TCK after the signal is applied to TMS. The TMS pin is powered
by the V
If the JTAG interface is not required on the board, you can disable the JTAG circuitry by
connecting this pin to logic high.
The clock input to the BST circuitry. Some operations occur at the rising edge, while
others occur at the falling edge. The TCK pin is powered by the V
I/O bank 8C.
It is expected that the clock input waveform have a nominal 50% duty cycle.
If the JTAG interface is not required on the board, you can disable the JTAG circuitry by
connecting TCK to GND.
Chapter 9: Configuration, Design Security, and Remote System Upgrades in Arria II GX Devices
CCIO
Pin Type
Input
Input
power supply of I/O bank 8C.
Optional pin that allows you to override all tri-states on the
device. When this pin is driven low, all I/O pins are tri-stated.
When this pin is driven high, all I/O pins behave as
programmed. Enable this pin by turning on the Enable
device-wide output enable (DEV_OE) option in the Quartus II
software.
Optional pin that allows you to override all clears on all device
registers. When this pin is driven low, all registers are cleared.
When this pin is driven high, all registers behave as
programmed. This pin is enabled by turning on the Enable
device-wide reset (DEV_CLRn) option in the Quartus II
software.
JTAG Boundary Scan Testing
Description
®
embedded logic array analyzer,
Description
CCIO
CCIO
power supply of I/O bank 8C.
© July 2010 Altera Corporation
power supply of I/O bank
chapter.
CCIO
Device Configuration Pins
power supply of