EP2AGX65DF29C6N Altera, EP2AGX65DF29C6N Datasheet - Page 83
EP2AGX65DF29C6N
Manufacturer Part Number
EP2AGX65DF29C6N
Description
IC ARRIA II GX FPGA 65K 780FBGA
Manufacturer
Altera
Series
Arria II GXr
Datasheets
1.EP2AGX45CU17C6N.pdf
(96 pages)
2.EP2AGX45CU17C6N.pdf
(14 pages)
3.EP2AGX45CU17C6N.pdf
(692 pages)
4.EP2AGX45CU17C6N.pdf
(10 pages)
5.EP2AGX45CU17C6N.pdf
(88 pages)
6.EP2AGX65DF29C6N.pdf
(306 pages)
Specifications of EP2AGX65DF29C6N
Number Of Logic Elements/cells
60214
Number Of Labs/clbs
2530
Total Ram Bits
5246
Number Of I /o
364
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
780-FBGA
Family Name
Arria® II GX
Number Of Logic Blocks/elements
63250
# I/os (max)
364
Frequency (max)
400MHz
Operating Supply Voltage (typ)
900mV
Logic Cells
63250
Ram Bits
5557452.8
Operating Supply Voltage (min)
0.87V
Operating Supply Voltage (max)
0.93V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
780
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP2AGX65DF29C6N
Manufacturer:
ST
Quantity:
12 000
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Chapter 4: DSP Blocks in Arria II GX Devices
Operational Mode Descriptions
Figure 4–13. Four-Multiplier Adder Mode Shown for Half-DSP Block
Note to
(1) Block output for accumulator overflow and saturate overflow.
High-Precision Multiplier Adder Mode
© July 2010
Figure
dataa_0[ ]
datab_0[ ]
dataa_1[ ]
datab_1[ ]
datab_2[ ]
dataa_3[ ]
datab_3[ ]
dataa_2[ ]
Altera Corporation
4–13:
In the high-precision multiplier adder, the DSP block can implement 2 two-multiplier
adders, with a multiplier precision of 18 × 36 (one two-multiplier adder per half-DSP
block). This mode is useful in filtering or fast Fourier transform (FFT) applications
where a datapath greater than 18 bits is required, yet 18 bits is sufficient for coefficient
precision. This can occur in cases where data has a high dynamic range. If the
coefficients are fixed, as in FFT and most filter applications, the precision of 18 bits
provides a dynamic range over 100 dB, if the largest coefficient is normalized to the
maximum 18-bit representation.
Half-DSP Block
clock[3..0]
ena[3..0]
aclr[3..0]
+
+
output_saturate
output_round
signa
signb
+
Arria II GX Device Handbook, Volume 1
overflow (1)
result[ ]
4–23
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