EP2AGX65DF29C6N Altera, EP2AGX65DF29C6N Datasheet - Page 226

• Manufacturer Part Number: EP2AGX65DF29C6N
• Description: IC ARRIA II GX FPGA 65K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX65DF29C6N

• Number Of Logic Elements/cells: 60214
• Number Of Labs/clbs: 2530
• Total Ram Bits: 5246
• Number Of I /o: 364
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 63250
• # I/os (max): 364
• Frequency (max): 400MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 63250
• Ram Bits: 5557452.8
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

9–6
Initialization
User Mode
Configuration Schemes
MSEL Pin Settings
Arria II GX Device Handbook, Volume 1
1
In Arria II GX devices, the initialization clock source is either the internal oscillator or
the optional CLKUSR pin. By default, the internal oscillator is the clock source for
initialization. If you use the internal oscillator, the Arria II GX device provides itself
with enough clock cycles for proper initialization. Therefore, if the internal oscillator
is the initialization clock source, sending the entire configuration file to the device is
sufficient to configure and initialize the device. Driving DCLK to the device after
configuration is complete does not affect device operation.
You also have the flexibility to synchronize initialization of multiple devices or to
delay initialization with the CLKUSR option. You can turn on the Enable
user-supplied start-up clock (CLKUSR) option in the Quartus II software from the
General tab of the Device and Pin Options dialog box. If you supply a clock on
CLKUSR, it does not affect the configuration process. After all the configuration data is
accepted and CONF_DONE goes high, CLKUSR is enabled after the time specified as
t
of clock cycles to initialize properly and enter user mode as specified in the t
parameter.
Two DCLK falling edges are required after CONF_DONE goes high to begin the
initialization of the device for both uncompressed and compressed bitstream in the
FPP or PS configuration mode.
An optional INIT_DONE pin is available, which signals the end of initialization and
the start of user-mode with a low-to-high transition. The Enable INIT_DONE Output
option is available in the Quartus II software from the General tab of the Device and
Pin Options dialog box. If you use the INIT_DONE pin, it is high due to an external
10-k pull-up resistor when nCONFIG is low and during the beginning of
configuration. After the option bit to enable INIT_DONE is programmed into the
device (during the first frame of configuration data), the INIT_DONE pin goes low.
When initialization is complete, the INIT_DONE pin is released and pulled high.
When initialization is complete, the device enters user mode. In user-mode, the user
I/O pins no longer have weak pull-up resistors and function as assigned in your
design.
The following sections describe configuration schemes for Arria II GX devices.
Select the configuration scheme by driving the Arria II GX device MSEL pins either
high or low, as shown in
power supply. Altera recommends you hardwire the MSEL[] pins to V
The MSEL[3..0] pins have 5-k internal pull-down resistors that are always active.
During POR and during reconfiguration, the MSEL pins must be at LVTTL V
levels to be considered logic low and logic high, respectively.
CD2CU
. After this time period elapses, Arria II GX devices require a minimum number
Chapter 9: Configuration, Design Security, and Remote System Upgrades in Arria II GX Devices
Table
9–2. The MSEL input buffers are powered by the V
© July 2010 Altera Corporation
Configuration Schemes
CCPD
or GND.
IL
CD2UMC
and V
CCPD
IH