EP2AGX65DF29C6N Altera, EP2AGX65DF29C6N Datasheet - Page 109

• Manufacturer Part Number: EP2AGX65DF29C6N
• Description: IC ARRIA II GX FPGA 65K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX65DF29C6N

• Number Of Logic Elements/cells: 60214
• Number Of Labs/clbs: 2530
• Total Ram Bits: 5246
• Number Of I /o: 364
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 63250
• # I/os (max): 364
• Frequency (max): 400MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 63250
• Ram Bits: 5557452.8
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

Chapter 5: Clock Networks and PLLs in Arria II GX Devices
PLLs in Arria II GX Devices
Clock Feedback Modes
© July 2010
Altera Corporation
1
Arria II GX PLLs support up to five clock feedback modes. Each mode allows clock
multiplication and division, phase shifting, and programmable duty cycle.
lists the clock feedback modes supported by the Arria II GX PLLs.
Table 5–9. Clock Feedback Mode Availability
Input and output delays are fully compensated by a PLL only when you use the
dedicated clock input pins associated with a given PLL as clock sources. For example,
when you use PLL_1 in normal mode, the clock delays from the input pin to the PLL
clock output-to-destination register are fully compensated, provided the clock input
pin is one of the following four pins: CLK12, CLK13, CLK14, or CLK15. When an
RCLK or GCLK network drives the PLL, the input and output delays may not be fully
compensated in the Quartus II software. Another example is when PLL_1 is
configured in zero delay buffer mode and the PLL input is driven by a dedicated clock
input pin, a fully compensated clock path results in zero delay between the clock
input and one of the output clocks from the PLL. If the PLL input is instead fed by a
non-dedicated input (using the GCLK network), the output clock may not be perfectly
aligned with the input clock.
Source-Synchronous Mode
If data and clock arrive at the same time on the input pins, the same phase
relationship is maintained at the clock and data ports of any IOE input register.
Figure 5–12
mode. This mode is recommended for source-synchronous data transfers. Data and
clock signals at the IOE experience similar buffer delays as long as you use the same
I/O standard.
Source-synchronous mode
No-compensation mode
Normal mode
Zero-delay buffer (ZDB) mode
LVDS compensation
Notes to
(1) ZDB mode uses 8 ns delay for compensation in Arria II GX devices.
(2) LVDS compensation mode is only supported on PLL_2, PLL_3, PLL_5, and PLL_6.
Table
shows an example waveform of the clock and data in source-synchronous
5–9:
Clock Feedback Mode
(1)
Availability in Arria II GX Devices
Arria II GX Device Handbook, Volume 1
Yes
Yes
Yes
Yes
Yes
(2)
Table 5–9
5–17