EP2AGX65DF29C6N Altera, EP2AGX65DF29C6N Datasheet - Page 161

• Manufacturer Part Number: EP2AGX65DF29C6N
• Description: IC ARRIA II GX FPGA 65K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX65DF29C6N

• Number Of Logic Elements/cells: 60214
• Number Of Labs/clbs: 2530
• Total Ram Bits: 5246
• Number Of I /o: 364
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 63250
• # I/os (max): 364
• Frequency (max): 400MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 63250
• Ram Bits: 5557452.8
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

Chapter 7: External Memory Interfaces in Arria II GX Devices
Arria II GX Memory Interfaces Pin Support
Figure 7–2. Memory Clock Generation
Notes to
(1) The mem_clk[0] and mem_clk_n[0] pins for DDR3, DDR2, and DDR SDRAM interfaces use the I/O input buffer for feedback; therefore,
(2) Global or regional clock networks are required for memory output clock generation to minimize jitter.
© July 2010 Altera Corporation
bidirectional I/O buffers are used for these pins. For memory interfaces with a differential DQS input, the input feedback buffer is configured as
differential input; for memory interfaces using a single-ended DQS input, the input buffer is configured as a single-ended input. Using a
single-ended input feedback buffer requires that the I/O standard’s V
Table
7–2:
System Clock
1
Memory clock pins in Arria II GX devices are generated with a DDIO register going to
differential output pins (refer to
DIFFIN or DIFFIO_RX prefixes in the pin table support the differential output
function and you can use them as memory clock pins.
Arria II GX devices offer differential input buffers for differential read-data strobe and
clock operations. In addition, Arria II GX devices also provide an independent DQS
logic block for each CQn pin for complementary read-data strobe and clock
operations. In the Arria II GX pin tables, the differential DQS pin pairs are denoted as
DQS and DQSn pins, and the complementary CQ signals are denoted as CQ and CQn
pins. DQSn and CQn pins are marked separately in the pin table. Each CQn pin
connects to a DQS logic block and the shifted CQn signals go to the negative-edge
input registers in the DQ I/O element registers.
DQ pins can be bidirectional signals, as in DDR3, DDR2, and DDR SDRAM, or
unidirectional signals, as in QDR II+/QDR II SRAM devices. Connect the
unidirectional read-data signals to Arria II GX DQ pins and the unidirectional
write-data signals to a different DQ/DQS group than the read DQ/DQS group. The
write clocks must be assigned to the DQS/DQSn pins associated to this write
DQ/DQS group. Do not use the CQ/CQn pin-pair for write clocks.
Using a DQ/DQS group for the write-data signals minimizes output skew and allows
vertical migration.
The DQ and DQS pin locations are fixed in the pin table. Memory interface circuitry is
available in every Arria II GX I/O bank that does not support transceivers. All
memory interface pins support the I/O standards required to support DDR3, DDR2,
DDR SDRAM, and QDR II+/QDR II SRAM devices.
V CC
(Note 1)
FPGA LEs
I/O Elements
REF
Figure
voltage is provided to that I/O bank’s VREF pins.
D
D
Q
Q
7–2). The Arria II GX pins marked with
1
0
Arria II GX Device Handbook, Volume 1
mem_clk (2)
mem_clk_n (2)
7–3