EP2AGX65DF29C6N Altera, EP2AGX65DF29C6N Datasheet - Page 104

• Manufacturer Part Number: EP2AGX65DF29C6N
• Description: IC ARRIA II GX FPGA 65K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX65DF29C6N

• Number Of Logic Elements/cells: 60214
• Number Of Labs/clbs: 2530
• Total Ram Bits: 5246
• Number Of I /o: 364
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 63250
• # I/os (max): 364
• Frequency (max): 400MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 63250
• Ram Bits: 5557452.8
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

5–12
Clock Source Control for PLLs
Cascading PLLs
Arria II GX Device Handbook, Volume 1
f
f
The clock input to Arria II GX PLLs comes from clock input multiplexers. The clock
multiplexer inputs come from dedicated clock input pins, PLLs through the GCLK
and RCLK networks, or from dedicated connections between adjacent corner and
center PLLs. The clock input sources to corner (PLL_1, PLL_2, PLL_3, PLL_4) and
center PLLs (PLL_5 and PLL_6) are shown in
The multiplexer select lines are set in the configuration file (.sof or .pof) only. When
configured, you cannot change this block without loading a new .sof or .pof. The
Quartus II software automatically sets the multiplexer select signals depending on the
clock sources selected in your design.
For more information about the clock control block and its supported features in the
Quartus II software, refer to the
Guide.
Figure 5–9. Clock Input Multiplexer Logic for Arria II GX PLLs
Notes to
(1) Input clock multiplexing is controlled through a configuration file (.sof or .pof) only; it cannot be dynamically
(2) Dedicated clock input pins to the PLLs, n=4 for PLL_4; n=4 or 8 for PLL_3; n=8 or 12 for PLL_2; and n=12 for
(3) You can drive the GCLK or RCLK clock input with an output from another PLL, a pin-driven GCLK or RCLK, or through
You can cascade the corner and center PLLs through the GCLK and RCLK networks.
In addition, where two PLLs exist next to each other, there is a direct connection
between them that does not require the GCLK and RCLK network. By cascading
PLLs, you can use this path to reduce clock jitter. The direct PLL cascading feature is
available in PLL_5 and PLL_6 on the right side of EP2AGX95, EP2AGX125,
EP2AGX190, and EP2AGX260 devices. Arria II GX devices allow cascading of PLL_1
and PLL_4 to the transceiver PLLs (clock management unit PLLs and receiver clock
data recoveries [CDRs]).
If your design cascades PLLs, the source (upstream) PLL must have a low-bandwidth
setting, while the destination (downstream) PLL must have a high-bandwidth setting.
For more information, refer to the “FPGA Fabric PLLs-Transceiver PLLs Cascading”
section in the
controlled when the device is operating in user mode.
PLL_1.
a clock control block, provided the clock control block is fed by an output from another PLL or a pin-driven dedicated
GCLK or RCLK. An internally generated global signal or general purpose I/O pin cannot drive the PLL.
Figure
GCLK / RCLK input (3)
Adjacent PLL output
5–9:
Arria II GX Transceiver Clocking
CLK[n+3..n] (2)
Clock Control Block (ALTCLKCTRL) Megafunction User
4
4
Chapter 5: Clock Networks and PLLs in Arria II GX Devices
chapter.
Figure
(1)
(1)
inclk0
inclk1
5–9.
Clock Networks in Arria II GX Devices
© July 2010 Altera Corporation
To the clock
switchover block