EP2AGX65DF29C6N Altera, EP2AGX65DF29C6N Datasheet - Page 49

• Manufacturer Part Number: EP2AGX65DF29C6N
• Description: IC ARRIA II GX FPGA 65K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX65DF29C6N

• Number Of Logic Elements/cells: 60214
• Number Of Labs/clbs: 2530
• Total Ram Bits: 5246
• Number Of I /o: 364
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 63250
• # I/os (max): 364
• Frequency (max): 400MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 63250
• Ram Bits: 5557452.8
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

Chapter 3: Memory Blocks in Arria II GX Devices
Memory Modes
Figure 3–9. Timing Waveform for Read-Write Operations (Single-Port Mode) for M9K
Figure 3–10.
© November 2009
q_a (asynch)
Timing Waveform for Read-Write Operations (Single-Port Mode) for MLAB
address_a
Altera Corporation
q_a (asynch)
data_a
clk_a
wrena
rdena
address_a
Figure 3–9
mode with unregistered outputs for M9K. Registering the M9K’s outputs would
simply delay the q output by one clock cycle.
Figure 3–10
mode with unregistered outputs for the MLAB. The read operation is triggered by the
rising clock edges whereas the write operation is triggered by the falling clock edges.
data_a
wrena
rdena
clk_a
shows timing waveforms for read and write operations in single-port
shows the timing waveforms for read and write operations in single-port
A
a0(old data)
(old data
A
a0
)
a0
B
A
a0
B
A
C
C
B
B
C
D
D
(old data)
a1(old data)
a1
a1
E
D
a1
E
Arria II GX Device Handbook, Volume 1
D
F
E
F
E
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