EP2AGX65DF29C6N Altera, EP2AGX65DF29C6N Datasheet - Page 63

• Manufacturer Part Number: EP2AGX65DF29C6N
• Description: IC ARRIA II GX FPGA 65K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX65DF29C6N

• Number Of Logic Elements/cells: 60214
• Number Of Labs/clbs: 2530
• Total Ram Bits: 5246
• Number Of I /o: 364
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 63250
• # I/os (max): 364
• Frequency (max): 400MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 63250
• Ram Bits: 5557452.8
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

Chapter 4: DSP Blocks in Arria II GX Devices
Simplified DSP Operation
Simplified DSP Operation
Figure 4–2. Basic Two-Multiplier Adder Building Block
© July 2010
Altera Corporation
A0[17..0]
B0[17..0]
A1[17..0]
B1[17..0]
The fundamental building block of Arria II GX devices is a pair of 18 × 18-bit
multipliers followed by a first-stage 37-bit addition and subtraction unit, as shown in
Equation 4–1
represented in 2’s complement format only.
Equation 4–1. Multiplier Equation
The structure shown in
such as complex multipliers and 36 × 36 multipliers, as described in later sections.
Each Arria II GX DSP block contains four two-multiplier adder units
(2 two-multiplier adder units per half block). Therefore, there are eight 18 × 18
multiplier functionalities per DSP block. For a detailed diagram of the DSP block,
refer to
Following the two-multiplier adder units are the pipeline registers, the second-stage
adders, and an output register stage. You can configure the second-stage adders to
provide the alternative functions shown in
block.
Equation 4–2. Four-Multiplier Adder Equation
Figure 4–4 on page
and
D
D
P[36..0] = A
Figure
Q
Q
Figure 4–2
4–2. For all signed numbers, input and output data is
4–7.
Z[37..0] = P
0
[17..0] × B
is useful for building more complex structures,
0
0
[17..0] ± A
[36..0] + P
Equation 4–1
+/-
1
1
[36..0]
[17..0] × B
and
Arria II GX Device Handbook, Volume 1
Equation 4–2
1
P[36..0]
[17..0]
per half
4–3