WG82574L S LBA9 Intel, WG82574L S LBA9 Datasheet - Page 81

• Manufacturer Part Number: WG82574L S LBA9
• Description: CONTROLLER, ENET, INTEL 82574L, 64PQFN
• Manufacturer: Intel

Specifications of WG82574L S LBA9

• Ethernet Type: IEEE 802.3, IEEE 802.3u, IEEE 802.3ab
• Supply Voltage Range: 3V To 3.6V
• Operating Temperature Range: 0°C To +85°C
• Digital Ic Case Style: QFN
• No. Of Pins: 64
• Package / Case: QFN
• Interface Type: I2C, JTAG, PCI, SPI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Initialization—82574 GbE Controller
4.6.5.1
4.6.6
Note:
Initialize the Receive Control Register
To properly receive packets requires simply that the receiver is enabled. This should be
done only after all other setup is accomplished. If software uses the Receive Descriptor
Minimum Threshold Interrupt, that value should be set.
The following should be done once per receive queue:
Transmit Initialization
Program the TXDCTL register with the desired TX descriptor write-back policy.
Suggested values are:
Program the TCTL register. Suggested configuration:
The following should be done once per transmit queue:
Note: the head and tail pointers are initialized (by hardware) to zero after a power-on
or a software-initiated device reset.
• Allocate a region of memory for the receive descriptor list.
• Receive buffers of appropriate size should be allocated and pointers to these
• Program the descriptor base address with the address of the region.
• Set the length register to the size of the descriptor ring.
• If needed, program the head and tail registers. Note: the head and tail pointers are
• The tail pointer should be set to point one descriptor beyond the end.
• GRAN = 1b (descriptors)
• WTHRESH = 1b
• All other fields 0b.
• CT = 0x0F
• COLD:
• PSP = 1b
• EN=1b
• All other fields 0b
• Allocate a region of memory for the transmit descriptor list.
• Program the descriptor base address with the address of the region.
• Set the length register to the size of the descriptor ring.
• If needed, program the head and tail registers.
buffers should be stored in the descriptor ring.
initialized (by hardware) to zero after a power-on or a software-initiated device
reset.
HDX = 511 (0x1FF); FDX = 63 (0x03F)
(16d collision)
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