WG82574L S LBA9 Intel, WG82574L S LBA9 Datasheet - Page 182

• Manufacturer Part Number: WG82574L S LBA9
• Description: CONTROLLER, ENET, INTEL 82574L, 64PQFN
• Manufacturer: Intel

Specifications of WG82574L S LBA9

• Ethernet Type: IEEE 802.3, IEEE 802.3u, IEEE 802.3ab
• Supply Voltage Range: 3V To 3.6V
• Operating Temperature Range: 0°C To +85°C
• Digital Ic Case Style: QFN
• No. Of Pins: 64
• Package / Case: QFN
• Interface Type: I2C, JTAG, PCI, SPI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

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The interrupt causes include:
In MSI-X mode the bits in this register can be configured to auto-clear when the MSI-X
interrupt message is sent, in order to minimize driver overhead, and when using MSI-X
interrupt signaling.
In systems that do not support MSI-X, reading the ICR register clears it's bits or writing
1b's clears the corresponding bits in this register.
Interrupt Cause Set Register (ICS)
This registers allows triggering an immediate interrupt by software, By writing 1b to
bits in ICS the corresponding bits in ICR is set Used usually to rearm interrupts the
software didn't have time to handle in the current interrupt routine.
Interrupt Mask Set and Read Register (IMS) and Interrupt Mask Clear
Register (IMC)
Interrupts appear on PCIe only if the interrupt cause bit is a one and the corresponding
interrupt mask bit is a one. Software blocks assertion of an interrupt by clearing the
corresponding bit in the mask register. The cause bit stores the interrupt event
regardless of the state of the mask bit. Clear and set make this register more thread
safe by avoiding a read-modify-write operation on the mask register. The mask bit is
set for each bit written to a one in the set register and cleared for each bit written in
the clear register. Reading the set register (IMS) returns the current mask register
value.
In MSI-X mode, CTRL_EXT. PBA_support should also be set. For more details see
section
Interrupt Auto Clear Enable Register (EIAC)
Bits 24:20 in this register enables clearing of the corresponding bit in ICR following
interrupt generation. When a bit is set, the corresponding bit in ICR and in IMS is
automatically cleared following an interrupt.
Used in MSI-X interrupt vector, this feature allows interrupt cause recognition, and
selective interrupt cause and mask bits reset, without requiring software to read the
ICR register, therefore, the penalty related to a PCIe read transaction is avoided.
Bits in the ICR that are not set in EIAC need to be cleared with ICR read or ICR write-
to-clear.
Interrupt Auto Mask Enable register (IAM)
In non MSI-X mode - Each bit in this register enables setting of the corresponding bit in
IMS following write to-clear to ICR.
In MSI-X mode and CTRL_EXT.EIAME is set, the software can set the bits of this
register to select mask bits that are cleared during interrupt processing. In this mode,
each bit in this register enables clearing of the corresponding bit in the mask register
(IM) following interrupt generation.
• The receive and transmit related interrupts (including new per queue cause).
• Other bits in this register are the legacy indication of interrupts as the MDIC
complete, management and link status change. There is a specific Other Cause bit
that is set if one of these bits are set, this bit can be mapped to a specific MSI-X
interrupt message.
10.2.2.5.
82574 GbE Controller—Inline Functions