WG82574L S LBA9 Intel, WG82574L S LBA9 Datasheet - Page 266

• Manufacturer Part Number: WG82574L S LBA9
• Description: CONTROLLER, ENET, INTEL 82574L, 64PQFN
• Manufacturer: Intel

Specifications of WG82574L S LBA9

• Ethernet Type: IEEE 802.3, IEEE 802.3u, IEEE 802.3ab
• Supply Voltage Range: 3V To 3.6V
• Operating Temperature Range: 0°C To +85°C
• Digital Ic Case Style: QFN
• No. Of Pins: 64
• Package / Case: QFN
• Interface Type: I2C, JTAG, PCI, SPI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

9.1.3.4
Figure 60.
9.1.3.5
266
Power Management Control/Status Register - (PMCSR), Offset 0xCC,
(RW)
This register is used to control and monitor power management events in the 82574.
Power Management Control/Status - PMCSR
PMCSR_BSE Bridge Support Extensions, Offset 0xCE, (RO)
This register is not implemented in the 82574, values set to 0x00.
15
14:13
12:9
8
7:4
3
2
1:0
Bits
0b at power up
see value in
Data register
0000b
0b at power up
000000b
0b
0b
00b
Default
R/W1C
RO
R/W
R/W
RO
RO
RO
R/W
Rd/Wr
PME_Status
This bit is set to 1b when the function detects a wake-up event
independent of the state of the PME_En bit. Writing a 1b clears this bit.
Data_Scale
This field indicates the scaling factor to be used when interpreting the
value of the Data register.
If the PM is enabled in the NVM, and the Data_Select field is set to 0, 3,
4 or7, than this field equals 01b (indicating 0.1 watt units). Else it
equals 00b.
Data_Select
This four-bit field is used to select which data is to be reported through
the Data register and Data_Scale field. These bits are writeable only
when power management is enabled via the NVM.
PME_En
If power management is enabled in the NVM, writing a 1b to this
register enables wake up.
If power management is disabled in the NVM, writing a 1b to this bit
has no affect, and does not set the bit to 1b.
Reserved
The 82574L returns a value of 000000b for this field.
No_Soft_Reset
This bit is always set to 0b to indicate that the 82574 performs an
internal reset upon transitioning from D3hot to D0 via software control
of the PowerState bits. Configuration context is lost when performing
the soft reset. Upon transition from the D3hot to the D0 state, a full re-
initialization sequence is needed to return the 82574 to the D0
Initialized state.
Reserved
Power State
This field is used to set and report the power state of the 82574 as
follows:
00b = D0.
01b = D1 (cycle ignored if written with this value).
10b = D2 (cycle ignored if written with this value).
11b = D3 (cycle ignored if PM is not enabled in the NVM).
82574 GbE Controller—Programing Interface
Description