WG82574L S LBA9 Intel, WG82574L S LBA9 Datasheet - Page 63

• Manufacturer Part Number: WG82574L S LBA9
• Description: CONTROLLER, ENET, INTEL 82574L, 64PQFN
• Manufacturer: Intel

Specifications of WG82574L S LBA9

• Ethernet Type: IEEE 802.3, IEEE 802.3u, IEEE 802.3ab
• Supply Voltage Range: 3V To 3.6V
• Operating Temperature Range: 0°C To +85°C
• Digital Ic Case Style: QFN
• No. Of Pins: 64
• Package / Case: QFN
• Interface Type: I2C, JTAG, PCI, SPI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Initialization—82574 GbE Controller
Table 29.
The resets affect the following registers and logic:
82574L Resets
Notes:
Reset
activation
PCIe Data Path
Load NVM
PCI Config
Registers RO
PCI Config
Registers RW
Data path
Wake Up (PM)
Context
Wake Up
Control
Register
Wake Up
Status
Registers
MNG Unit
Wake Up
Management
Registers
PHY
Strapping Pins
1. If D3cold is not supported, the wake-up context is reset (PME_Status and PME_En
2. Refers to bits in the Wake-Up Control (WUC) register that are not part of the wake-
3. The Wake-Up Status (WUS) registers include the following:
• Force TCO - This reset is generated when manageability logic is enabled. It is only
• EEPROM Reset - Writing a 1b to the EEPROM Reset bit of the Extended Device
• PHY Reset - Software can write a 1b to the PHY Reset bit of the Device Control
generated if the reset on the Force TCO bit of the NVM's Management Control word
is 1b. In pass-through mode it is generated when receiving a Force TCO SMBus
command with bit 1 or bit 7 set.
Control (CTRL_EXT.EE_RST) register causes the 82574 to re-read the per-function
configuration from the NVM, setting the appropriate bits in the registers loaded by
the NVM.
(CTRL.PHY_RST) register to reset the internal PHY.
bits).
up context (the PME_En and PME_Status bits).
— WUS register.
— Wake-up packet length.
— Wake-up packet memory.
Internal
Power
On
Reset












PE_
RST_
N
1








Device/Dr
Disable












In-band
PCIe
Reset
Reset Name








D3hot
D0
6




SW
Reset



Force
TCO




EE
Reset

PHY
Reset

Notes
5
2
3
4
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