WG82574L S LBA9 Intel, WG82574L S LBA9 Datasheet - Page 271

• Manufacturer Part Number: WG82574L S LBA9
• Description: CONTROLLER, ENET, INTEL 82574L, 64PQFN
• Manufacturer: Intel

Specifications of WG82574L S LBA9

• Ethernet Type: IEEE 802.3, IEEE 802.3u, IEEE 802.3ab
• Supply Voltage Range: 3V To 3.6V
• Operating Temperature Range: 0°C To +85°C
• Digital Ic Case Style: QFN
• No. Of Pins: 64
• Package / Case: QFN
• Interface Type: I2C, JTAG, PCI, SPI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Programing Interface—82574 GbE Controller
9.1.6
9.1.6.1
Table 76.
9.1.6.1.1
9.1.6.1.2
9.1.6.1.3
PCIe Configuration Registers
PCIe provides two mechanisms to support native features:
Initialization values of the configuration registers are marked in parenthesis.
PCIe Capability Structure
The 82574L implements the PCIe capability structure for end-point devices as listed in
Table
PCIe Configuration Registers
Capability ID, Offset 0xE0, (RO)
This field equals 0x10 indicating the linked list item as being the PCIe Capabilities
registers.
Next Pointer, Offset 0xE1, (RO)
Offset to the next capability item in the capability list. A value of 0xA0 points to the
MSI-X capability.
PCI Express CAP, Offset 0xE2, (RO)
The PCIe capabilities register identifies PCIe device type and associated capabilities.
This is a read-only register.
3:0
7:4
8
13:9
15:14
• PCIe defines a PCIe capability pointer indicating support for PCIe.
• PCIe extends the configuration space beyond the 256 bytes available for PCI to
Byte Offset
Bits
4096 bytes.
0xEC
0xE0
0xE4
0xE8
0xF0
76:
0001b
0000b
0b
00000b
00b
Default
RO
RO
RO
RO
RO
R/W
Byte 3
PCIe Capability Register
Device Status
Capability Version
Indicates the PCIe capability structure version number 1.
Device/Port Type
Indicates the type of PCIe functions. LAN function in the 82574 is a native
PCIe functions with a value of 0000b.
Slot Implemented
The 82574L does not implement slot options therefore this field is hardwired
to 0b.
Interrupt Message Number
The 82574L does not implement multiple MSI per function, therefore this field
is hardwired to 0x0.
Reserved
Link Status
Byte 2
Device Capability
Link Capability
Description
Next Pointer
Byte 1
Device Control
Link Control
Capability ID
Byte 0
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