WG82574L S LBA9 Intel, WG82574L S LBA9 Datasheet - Page 403

• Manufacturer Part Number: WG82574L S LBA9
• Description: CONTROLLER, ENET, INTEL 82574L, 64PQFN
• Manufacturer: Intel

Specifications of WG82574L S LBA9

• Ethernet Type: IEEE 802.3, IEEE 802.3u, IEEE 802.3ab
• Supply Voltage Range: 3V To 3.6V
• Operating Temperature Range: 0°C To +85°C
• Digital Ic Case Style: QFN
• No. Of Pins: 64
• Package / Case: QFN
• Interface Type: I2C, JTAG, PCI, SPI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Driver Programing Interface—82574 GbE Controller
10.2.11.22 Bias Setting Register 1 (Page 0), PHY Address 01; Register 29
10.2.11.23 Bias Setting Register 2 (Page 0), PHY Address 01; Register 30
10.2.11.24 MAC Specific Control Register 1 (Page 2), PHY Address 01; Register 16
15:0
15:0
15:14
13:10
9
8
7
6:4
3
2:0
Bits
Bits
Bits
Bias setting1
Bias setting2
Transmit
FIFO Depth
Reserved
Disable
fi_125_clk
Disable
fi_50_clk
Reserved
Reserved
GMII
Interface
Power
Down
Reserved
Field
Field
Field
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Mode
R/W
R/W
Mode
Mode
0x0
0x00
See
Description
See
Description
0x1
0x0
0x1
0x0
HW Rst
HW Rst
HW Rst
Retain
Retain
Retain
Update
SW Rst
Retain
Update
Retain
Retain
Retain
Retain
SW Rst
SW Rst
1000BASE-T:
00b = ± 16 bits.
01b = ± 24 bits.
10b = ± 32 bits.
11b = ± 40 bits.
Reserved, set to 0x00.
Changes to this bit are disruptive to the normal
operation; therefore, any changes to these registers
must be followed by a software reset to take effect.
After a hardware reset, this bit takes on the value of
pd_pwrdn_clk125_a. When pd_pwrdn_clk125_a
transitions from one to zero this bit is set to 0b. When
pd_pwrdn_clk125_a transitions from zero to one this
bit is set to 1b.
1b = fi_125_clk low.
0b = fi_125_clk toggle
After a hardware reset, this bit takes on the value of
pd_pwrdn_clk50_a. When pd_pwrdn_clk50_a
transitions from one to zero this bit is set to 0b. When
pd_pwrdn_clk50_a transitions from zero to one this
bit is set to 1b.
1b = fi_50_clk low.
0b = fi_50_clk toggle.
Reserved, write as 0x1.
Reserved, write as 0x00.
Changes to this bit are disruptive to the normal
operation; therefore, any changes to these registers
must be followed by a software reset to take effect.
This bit determines whether the GMII RX_CLK powers
down when register 0.11, 16_0.2 are used to power
down the 82574 or when the PHY enters the energy
detect state.
1b = Always power up.
0b = Can power down.
Reserved, write as 0x00.
Used to optimize PHY performance in
1000Base-T mode. Set to 0x0003 when
initializing the 82574 to improve BER
performance.
Used to optimize PHY performance in
1000Base-T mode. Set to 0x0000 when
initializing the 82574 to improve BER
performance.
Description
Description
Description
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