WG82574L S LBA9 Intel, WG82574L S LBA9 Datasheet - Page 353

• Manufacturer Part Number: WG82574L S LBA9
• Description: CONTROLLER, ENET, INTEL 82574L, 64PQFN
• Manufacturer: Intel

Specifications of WG82574L S LBA9

• Ethernet Type: IEEE 802.3, IEEE 802.3u, IEEE 802.3ab
• Supply Voltage Range: 3V To 3.6V
• Operating Temperature Range: 0°C To +85°C
• Digital Ic Case Style: QFN
• No. Of Pins: 64
• Package / Case: QFN
• Interface Type: I2C, JTAG, PCI, SPI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Driver Programing Interface—82574 GbE Controller
10.2.7.3
10.2.7.4
Note:
10.2.7.5
10.2.7.6
Counts the number of receive packets with alignment errors (such as the packet is not
an integer number of bytes in length). In order for a packet to be counted in this
register, it must pass address filtering and must be 64 bytes or greater (from
<Destination Address> through <CRC>, inclusively) in length. If receives are not
enabled, then this register does not increment. This register is valid only in MII mode
during 10/100 Mb/s operation.
RX Error Count - RXERRC (0x0400C; R)
Counts the number of packets received in which RX_ER was asserted by the PHY. In
order for a packet to be counted in this register, it must pass address filtering and must
be 64 bytes or greater (from <Destination Address> through <CRC>, inclusively) in
length. If receives are not enabled, then this register does not increment.
Missed Packets Count - MPC (0x04010; R)
Counts the number of missed packets. Packets are missed when the receive FIFO has
insufficient space to store the incoming packet. This could be caused because of too
few buffers allocated, or because there is insufficient bandwidth on the IO bus. Events
setting this counter cause RXO, the receiver overrun interrupt, to be set. This register
does not increment if receives are not enabled.
Note that these packets are also counted in the Total Packets Received register as well
as in the Total Octets Received register.
Single Collision Count - SCC (0x04014; R)
This register counts the number of times that a successfully transmitted packet
encountered a single collision. This register only increments if transmits are enabled
and the device is in half-duplex mode.
Excessive Collisions Count - ECOL (0x04018; R)
RXEC
MPC
SCC
ECC
Field
Field
Field
Field
31:0
31:0
31:0
31:0
Bit(s)
Bit(s)
Bit(s)
Bit(s)
0x0
0x0
0x0
0x0
Initial
Initial
Initial
Initial
Value
Value
Value
Value
RX Error Count
Missed Packets Count
Number of times a transmit encountered a single collision.
Number of packets with more than 16 collisions.
Description
Description
Description
Description
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