WG82574L S LBA9 Intel, WG82574L S LBA9 Datasheet - Page 313

• Manufacturer Part Number: WG82574L S LBA9
• Description: CONTROLLER, ENET, INTEL 82574L, 64PQFN
• Manufacturer: Intel

Specifications of WG82574L S LBA9

• Ethernet Type: IEEE 802.3, IEEE 802.3u, IEEE 802.3ab
• Supply Voltage Range: 3V To 3.6V
• Operating Temperature Range: 0°C To +85°C
• Digital Ic Case Style: QFN
• No. Of Pins: 64
• Package / Case: QFN
• Interface Type: I2C, JTAG, PCI, SPI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Driver Programing Interface—82574 GbE Controller
L1_act_
without_L0s_
rx
L1_Entry_
Latency (LSB)
(Read Only)
L0S_ENTRY_
LAT
L1_Entry_
Latency (MSB)
(Read Only)
Reserved
Header_log_
order
PBA_CL_DEAS 20
Reserved
Rx_L0s_
Adjustment
Reserved
TXDSCR_
NOSNOOP
TXDSCW_
NOSNOOP
TXD_
NOSNOOP
RXDSCR_
NOSNOOP
RXDSCW_
NOSNOOP
RXD_
NOSNOOP
Field
27
26:25
24
23
22
21
19:10
9
8:6
5
4
3
2
1
0
Bit(s)
0b
11b
0b
1b
0b
0b
0b
0x0
1b
0b
0b
0b
0b
0
0b
0b
Initial
Value
If set, enables the device to enter ASPM L1 active without any
correlation to L0s_rx.
Determines the idle time of the PCIe link in L0s state before initiating
a transition to L1 state. The initial value is loaded from NVM.
00b = 64 s
01b = 256 s
10b = 1 ms
11b = 4 ms
L0s Entry Latency
Set to 0b to indicate L0s entry latency is the same as L0s exit latency.
Set to 1b to indicate L0s entry latency is (L0s exit latency/4).
Latency
000b = 2 s.
001b = 8 s.
010b = 1 6s.
011b = 32 s.
100b = 64 s.
101b = 25 6s.
110b = 1 ms.
111b = 4 ms (default).
Reserved
For proper operation, must be set to 1b by software during
initialization.
When set, indicates a need to change the order of the header log in
the error reporting registers.
If cleared, PBA is cleared on de-assertion of MSI-X request.
Reserved
When set to 1b the reply-timer always adds the required L0s
adjustment. When cleared to 0b the adjustment is added only when
Tx L0s is active.
Reserved
Transmit Descriptor Read – No Snoop Indication.
Read directly by transaction layer.
Transmit Descriptor Write – No Snoop Indication.
Read directly by transaction layer.
Transmit Data Read – No Snoop Indication.
Read directly by transaction layer.
Receive Descriptor Read – No snoop indication.
Read directly by transaction layer.
Receive Descriptor Write – No Snoop Indication
Read directly by transaction layer.
Receive Data Write – No Snoop Indication
Read directly by transaction layer.
Description
313