WG82574L S LBA9 Intel, WG82574L S LBA9 Datasheet - Page 194
WG82574L S LBA9
Manufacturer Part Number
WG82574L S LBA9
Description
CONTROLLER, ENET, INTEL 82574L, 64PQFN
Manufacturer
Intel
Datasheet
1.WG82574IT_S_LBAC.pdf
(490 pages)
Specifications of WG82574L S LBA9
Ethernet Type
IEEE 802.3, IEEE 802.3u, IEEE 802.3ab
Supply Voltage Range
3V To 3.6V
Operating Temperature Range
0°C To +85°C
Digital Ic Case Style
QFN
No. Of Pins
64
Package / Case
QFN
Interface Type
I2C, JTAG, PCI, SPI
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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Figure 43.
7.7.3.3
194
On the Rx this logic parses the traversing frame and if Rx timestamp is enabled and it
matches the Ethertype, UDP port (if needed), version and message type as defined in
the register described in
latched in the timestamp registers. In addition two indications in the Rx descriptor are
added, one to identify that this is a PTP packet (done with packet type, this is only for
L2 packets since on the UDP packets the port number directs the packet to the
application) and the second (TS) to identify that a time stamp was taken for this
packet. If a PTP packet is received but does not match time stamping criteria (not an
event packet) or for some reason time stamp was not taken only the first indication is
added.
For more details please refer to the time stamp registers sections
section
should be captured.
On both sides the time stamp values are locked in the registers until software access.
This means that if a new PTP packet that requires time stamp has arrived before
software accessed the previous PTP packet, the new PTP packet is not time stamped. In
some cases on the RX path a packet that was time stamped might be lost and not get
to the host, to avoid lock condition the software should keep a watch dog timer to clear
locking of the time stamp register. The value of such timer should be at least higher
then the expected interval between two Sync or Delay_Req packets (depends on
master or slave).
Time Stamp Point
Time Adjustment Mode of Operation
Node in time sync network can be in one of two states master or slave. When a time
sync entity is at master state it should synchronize other entities to its system clock. In
this case no time adjustments are needed. When the entity is in slave state it should
adjust its system clock by using the data arrived with the Follow_Up and
Delay_Response packets and to the time stamp values of Sync and Delay_Req packets.
When having all the values, software on the slave entity can adjust its offset in the
following manner.
10.2.9.1). The following figure defines the exact point where the time value
section 10.2.9.7
the time, sourceId and sequenceId are
82574 GbE Controller—Inline Functions
(section 10.2.9.8
or
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