WG82574L S LBA9 Intel, WG82574L S LBA9 Datasheet - Page 359

• Manufacturer Part Number: WG82574L S LBA9
• Description: CONTROLLER, ENET, INTEL 82574L, 64PQFN
• Manufacturer: Intel

Specifications of WG82574L S LBA9

• Ethernet Type: IEEE 802.3, IEEE 802.3u, IEEE 802.3ab
• Supply Voltage Range: 3V To 3.6V
• Operating Temperature Range: 0°C To +85°C
• Digital Ic Case Style: QFN
• No. Of Pins: 64
• Package / Case: QFN
• Interface Type: I2C, JTAG, PCI, SPI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Driver Programing Interface—82574 GbE Controller
10.2.7.26
10.2.7.27
10.2.7.28
10.2.7.29
10.2.7.30
Broadcast Packets Received Count - BPRC (0x04078; R)
This register counts the number of good (non-erred) broadcast packets received. This
register does not count broadcast packets received when the broadcast address filter is
disabled. This register only increments if receives are enabled.
Multicast Packets Received Count - MPRC (0x0407C; R)
This register counts the number of good (non-erred) multicast packets received. This
register does not count multicast packets received that fail to pass address filtering nor
does it count received flow control packets. This register only increments if receives are
enabled. This register does not count packets counted by the Missed Packet Count
(MPC) register.
Good Packets Transmitted Count - GPTC (0x04080; R)
This register counts the number of good (non-erred) packets transmitted. A good
transmit packet is considered one that is 64 or more bytes in length (from <Destination
Address> through <CRC>, inclusively) in length. This does not include transmitted flow
control packets. This register only increments if transmits are enabled. This register
does not count packets counted by the Missed Packet Count (MPC) register. The
register counts clear as well as secure packets.
Good Octets Received Count - GORCL (0x04088; R)
Good Octets Received Count - GORCH (0x0408C; R)
These registers make up a logical 64-bit register that counts the number of good (non-
erred) octets received. This register includes bytes received in a packet from the
<Destination Address> field through the <CRC> field, inclusively. This register must be
accessed using two independent 32-bit accesses. This register resets whenever the
upper 32 bits are read (GORCH).
BPRC
MPRC
GPTC
GORCL
GORCH
Field
Field
Field
Field
31:0
31:0
31:0
31:0
31:0
Bit(s)
Bit(s)
Bit(s)
Bit(s)
0x0
0x0
0x0
0x0
0x0
Initial
Initial
Initial
Initial
Value
Value
Value
Value
Number of broadcast packets received.
Number of multicast packets received.
Number of good packets transmitted.
Number of good octets received – lower 4 bytes.
Number of good octets received – upper 4 bytes.
Description
Description
Description
Description
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