WG82574L S LBA9 Intel, WG82574L S LBA9 Datasheet - Page 416

• Manufacturer Part Number: WG82574L S LBA9
• Description: CONTROLLER, ENET, INTEL 82574L, 64PQFN
• Manufacturer: Intel

Specifications of WG82574L S LBA9

• Ethernet Type: IEEE 802.3, IEEE 802.3u, IEEE 802.3ab
• Supply Voltage Range: 3V To 3.6V
• Operating Temperature Range: 0°C To +85°C
• Digital Ic Case Style: QFN
• No. Of Pins: 64
• Package / Case: QFN
• Interface Type: I2C, JTAG, PCI, SPI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

10.2.12.13 Packet Buffer Size -PBS (0x01008; RW)
Note:
Note:
416
All PBM (FIFO) data is available to diagnostics. Locations can be accessed as 32-bit or
64-bit words. The internal PBM is 40 KB in size. As mentioned in
software can configure the amount of PBM space that is used as the transmit FIFO
versus the receive FIFO. The default is 16 KB of transmit FIFO space and 16 KB of
receive FIFO space. Regardless of the individual FIFO sizes that software configures,
the RX FIFO is located first in the memory mapped PBM space. So for the default FIFO
configuration, the RX FIFO occupies offsets 0x10000-0x13FFF of the memory mapped
space, while the TX FIFO occupies offsets 0x14000-0x17FFF of the memory mapped
space.
This register sets the on-chip receive and transmit storage allocation size, The
allocation value is read/write for the lower six bits. The division between transmit and
receive is done according to the PBA register.
Programming this register does not automatically re-load or initialize internal packet-
buffer RAM pointers. The software must reset both transmit and receive operation
(using the global device reset CTRL.RST bit) after changing this register in order for it
to take effect. The PBS register itself is not reset by asserting the global reset, but only
is reset at initial hardware power on.
Programming this register should be aligned with programming the PBA register. If PBA
and PBS are not coordinated, hardware operation is not determined.
PBS
Rsvd
Field
15:0
31:16
Bit(s)
0x0028
0x0000
Initial
Value
Packet Buffer Size
Lower six bits declare the packet buffer size both for transmit and
receive in 1 KB granularity. The upper 10 bits are read as zero. The
default is 40 KB.
Reserved read as zero.
82574 GbE Controller—Driver Programing Interface
Description
Section
10.2.7.36,